ST68C554 datasheet(23/40 Pages) EXAR

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ST16C554/554D/68C554

Rev. 3.10

have a valid stop bit(s). In the FIFO mode this error is

associated with the character at the top of the FIFO.

LSR BIT-4:

Logic 0 = No break condition. (normal default condi-

tion)

Logic 1 = The receiver received a break signal (RX

was a logic 0 for one character frame time). In the

FIFO mode, only one break character is loaded into

the FIFO.

LSR BIT-5:

This bit is the Transmit Holding Register Empty indi-

cator. This bit indicates that the UART is ready to

accept a new character for transmission. In addition,

this bit causes the UART to issue an interrupt to CPU

when the THR interrupt enable is set. The THR bit is

set to a logic 1 when a character is transferred from the

transmit holding register into the transmitter shift

loading of the transmitter holding register by the CPU.

In the FIFO mode this bit is set when the transmit FIFO

is empty; it is cleared when at least 1 byte is written to

the transmit FIFO.

LSR BIT-6:

This bit is the Transmit Empty indicator. This bit is set

to a logic 1 whenever the transmit holding register and

the transmit shift register are both empty. It is reset to

logic 0 whenever either the THR or TSR contains a

data character. In the FIFO mode this bit is set to one

whenever the transmit FIFO and transmit shift register

are both empty.

LSR BIT-7:

Logic 0 = No Error. (normal default condition)

Logic 1 = At least one parity error, framing error or

break indication is in the current FIFO data. This bit is

cleared when LSR register is read.

Modem Status Register (MSR)

This register provides the current state of the control

interface signals from the modem, or other peripheral

device that the 554D is connected to. Four bits of this

These bits are set to a logic 1 whenever a control input

from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

MSR BIT-0:

Logic 0 = No -CTS Change (normal default condition)

Logic 1 = The -CTS input to the 554D has changed

state since the last time it was read. A modem Status

Interrupt will be generated.

MSR BIT-1:

Logic 0 = No -DSR Change. (normal default condition)

Logic 1 = The -DSR input to the 554D has changed

state since the last time it was read. A modem Status

Interrupt will be generated.

MSR BIT-2:

Logic 0 = No -RI Change. (normal default condition)

Logic 1 = The -RI input to the 554D has changed from

a logic 0 to a logic 1. A modem Status Interrupt will be

generated.

MSR BIT-3:

Logic 0 = No -CD Change. (normal default condition)

Logic 1 = Indicates that the -CD input to the has

changed state since the last time it was read. A

modem Status Interrupt will be generated.

MSR BIT-4:

-CTS (active high, logical 1). Normally MSR bit-4 bit

is the compliment of the -CTS input. However in the

loopback mode, this bit is equivalent to the RTS bit in

the MCR register.

MSR BIT-5:

DSR (active high, logical 1). Normally this bit is the

compliment of the -DSR input. In the loopback mode,

this bit is equivalent to the DTR bit in the MCR register.

MSR BIT-6:

RI (active high, logical 1). Normally this bit is the

compliment of the -RI input. In the loopback mode this

bit is equivalent to the OP1 bit in the MCR register.

ST68C554 数据表(PDF) 23 Page - Exar Corporation

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