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数据搜索系统，热门电子元器件搜索 |
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ST68C554 数据表(PDF) 24 Page - Exar Corporation |
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ST68C554 数据表(HTML) 24 Page - Exar Corporation |
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24 / 40 page  ST16C554/554D/68C554 24 Rev. 3.10 MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loopback mode this bit is equivalent to the OP2 bit in the MCR register. Scratchpad Register (SPR) The ST16C554D provides a temporary data register to store 8 bits of user information. ST16C554D EXTERNAL RESET CONDITIONS REGISTERS RESET STATE IER IER BITS 0-7=0 ISR ISR BIT-0=1, ISR BITS 1-7=0 LCR LCR BITS 0-7=0 MCR MCR BITS 0-7=0 LSR LSR BITS 0-4=0, LSR BITS 5-6=1 LSR, BIT 7=0 MSR MSR BITS 0-3=0, MSR BITS 4-7= input signals FCR FCR BITS 0-7=0 SIGNALS RESET STATE TX A-D High -RTS A-D High -DTR A-D High -RXRDY High -TXRDY Low |
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