Data Sheet

AD8363

Table 6. Evaluation Board Configuration Options

Component

Function/Notes

Default Value

C6, C10,

C11, C12

Input. The AD8363 is single-ended driven. At frequencies ≤2.6 GHz, the best dynamic range is achieved by

driving Pin 14 (INHI). When driving INHI, populate C10 and C12 with an appropriate capacitor value for the

frequency of operation and leave C6 and C11 open. For frequencies >2.6 GHz, additional dynamic range

can be achieved by driving Pin 15 (INLO). When driving INLO, populate C6 and C11 with an appropriate

capacitor value for the frequency of operation and leave C10 and C12 open.

C6 = open,

C10 = 0.1 µF,

C11 = open

C12 = 0.1 µF

R7, R8, R10,

R11

VTGT. R10 and R11 are set up to provide 1.4 V to VTGT from VREF. If R10 and R11 are removed, an external

voltage can be used. Alternatively, R7 and R11 can be used to form a voltage divider for an external

reference.

R7 = 0 Ω,

R8 = 0 Ω,

R10 = 845 Ω,

R11 = 1.4 kΩ

C4, C5, C7,

C13, R14, R16

Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed

physically close to the AD8363, a 0 Ω series resistor, and a 0.1 µF capacitor placed close to the power

supply input pin. The 0 Ω resistor can be replaced with a larger resistor to add more filtering; however, it is

at the expense of a voltage drop.

C4 = 100 pF,

C5 = 100 pF,

C7 = 0.1µF,

C13 = 0.1µF,

R14 = 0 Ω,

R16 = 0 Ω

R1, R2, R6,

R13, R15

Output Interface (Default Configuration) in Measurement Mode. In this mode, a portion of the output

voltage is fed back to the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude

of the slope at VOUT is increased by reducing the portion of VOUT that is fed back to VSET. If a fast

responding output is expected, the 0 Ω resistor (R15) can be removed to reduce parasitics on the output.

R1 = 0 Ω,

R2 = open,

R6 = 0 Ω,

R13 = open,

R15 = 0 Ω

Output Interface in Controller Mode. In this mode, R6 must be open and R13 must have a 0 Ω resistor. In

controller mode, the AD8363 can control the gain of an external component. A setpoint voltage is applied

to the VSET pin, the value of which corresponds to the desired RF input signal level applied to the AD8363.

If a fast responding output is expected, the 0 Ω resistor (R15) can be removed to reduce parasitics on the output.

C8, C9, R5

should be 390 pF. R5, when set to a value other than 0 Ω, is used in conjunction with C8 and C9 to modify

the loop transfer function and change the loop dynamics in controller mode.

C8 = open,

C9 = 0.1 µF,

R5 = 0 Ω

C3

when used. No capacitor is needed for input frequencies greater than 10 MHz.

C3 = open

R9, R12

TCM2/PWDN. The TCM2/PWDN pin controls the amount of nonlinear intercept temperature compensation

and/or shuts down the device. The evaluation board is configured to control this from a test loop, but VREF

can also be used by the voltage divider created by R9 and R12.

R9 = open,

R12 = open

R17, R18

TCM1. TCM1 controls the temperature compensation (5 kΩ impedance). The evaluation board is configured to

control this from a test loop, but VREF can also be used by the voltage divider created by R17 and R18. Due

to the relatively low impedance of the TCM1 pin and the limited current of the VREF pin, care should be

taken when choosing the R17 and R18 values.

R17 = open,

R18 = open

Paddle

Connect the paddle to both a thermal and electrical ground.

Rev. B | Page 27 of 29