AD8363ACPZ-R2 datasheet(20/29 Pages) AD

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AD8363

Data Sheet

Rev. B | Page 20 of 29

–3

–1

–2

–60

–50

–40

–30

–20

–10

PIN (dBm)

INHI INPUT

VTCM1 = 0.52V, VTCM2 = 0.6V

–40°C

+25°C

+85°C

+125°C

Figure 46. VOUT and Log Conformance Error vs. Input Amplitude at 2.14 GHz,

−40°C to +125°C

OUTPUT VOLTAGE SCALING

The output voltage range of the AD8363 (nominally 0 V to

3.5 V) can be easily increased or decreased. There are a number

of situations where adjustment of the output scaling makes

sense. For example, if the AD8363 is driving an analog-to-

digital converter (ADC) with a 0 V to 5 V input range, it makes

sense to increase the detector’s nominal maximum output

voltage of 3.5 V so that it is closer to 5 V. This makes better use

of the input range of the ADC and maximizes the resolution of

the system in terms of bits/dB.

If only a part of the RF input power range of the AD8363 is

being used (for example, −10 dBm to −40 dBm), it may make

sense to increase the scaling so that this reduced input range fits

into the available output swing of the AD8363 (0 V to 4.8 V).

The output swing can be reduced by adding a voltage divider on

the output pin, as shown in Figure 47 (with VOUT connected

directly to VSET and a resistor divider on VOUT). Figure 47

also shows how the output voltage swing can be increased using

a technique that is analogous to setting the gain of an op amp in

noninverting mode. With the VSET pin being the equivalent of

the inverting input of the op amp, a resistor divider is connected

between VOUT and VSET.

VSET

VOUT

VSET

VOUT

Figure 47. Decreasing and Increasing Slope

Equation 17 is the general function that governs this.

















)

(

(17)

where:

VO is the nominal maximum output voltage (see Figure 4

through Figure 18).

V'O is the new maximum output voltage (for example, up to

4.8 V).

RIN is the VSET input resistance (72 kΩ).

When choosing R1 and R2, attention must be paid to the

current drive capability of the VOUT pin and the input

resistance of the VSET pin. The choice of resistors should not

result in excessive current draw out of VOUT. However, making

R1 and R2 too large is also problematic. If the value of R2 is

compatible with the 72 kΩ input resistance of the VSET input,

this input resistance, which varies slightly from device to device,

contributes to the resulting slope and output voltage. In general,

the value of R2 should be at least ten times smaller than the

input resistance of VSET. Values for R1 and R2 should, therefore,

be in the 1 kΩ to 5 kΩ range.

It is also important to take into account device-to-device and

frequency variation in output swing along with the AD8363

output stage’s maximum output voltage of 4.8 V. The VOUT

distribution is well characterized at the bands of major

frequencies in the Typical Performance Characteristics section

(Figure 3 to Figure 18).

OFFSET COMPENSATION, MINIMUM CLPF, AND

MAXIMUM CHPF CAPACITANCE VALUES

An offset-compensation loop is used to eliminate small dc

offsets within the internal VGA as shown in Figure 48. The

high-pass corner frequency of this loop is set to about 1 MHz

using an on-chip 25 pF capacitor. Because input signals that are

below 1 MHz are interpreted as unwanted offset voltages, this

restricts the operating frequency range of the device. To operate the

AD8363 at lower frequencies (than 1 MHz), the high-pass corner

frequency must be reduced by connecting a capacitor between

CHPF and VPOS.

Internal offset voltages vary depending on the gain at which the

VGA is operating and, therefore, on the input signal amplitude.

When a large CHPF value is used, the offset correction process can

lag the more rapid changes in the gain of the VGA, which can

increase the time required for the loop to fully settle for a given

steady input amplitude. This can manifest itself in a jumpy,

seemingly oscillatory response of the AD8363.

Care should therefore be taken in choosing CHPF and CLPF

because there is a potential to create oscillations. In general, make

the capacitance on the CLPF pin as large as possible; there is no

maximum on the amount of capacitance that can be added to

this pin. At high frequencies, there is no need for an external

capacitor on the CHPF pin; therefore, the pin can be left open.

However, when trying to get a fast response time and/or when

working at low frequencies, extra care in choosing the proper

capacitance values for CHPF and CLPF is prudent. With the gain

control pin (VSET) connected to VOUT, VSET can slew at a rate

determined by the on-chip squaring cell and CLPF. When VSET is

changing with time, the dc offsets in the VGA also vary with

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