AD8363ACPZ-R2 datasheet(17/29 Pages) AD

17 / 29 page

Data Sheet

AD8363

Rev. B | Page 17 of 29

over a population of devices to be useful in mass production

applications.

The TCM1 and TCM2 pins have high input impedances,

approximately 5 kΩ and 500 kΩ, respectively, and can be

conveniently driven from an external source or from a fraction

of VREF by using a resistor divider. VREF does change slightly

with temperature and RF input amplitude (see Figure 32 and

Figure 29); however, the amount of change is unlikely to result

in a significant effect on the final temperature stability of the RF

measurement system.

Figure 38 shows a simplified schematic representation of TCM1.

See the Power-Down Interface section for the TCM2 interface.

3kΩ

ESD

VPOS

COMM

TCM1

Figure 38. TCM1 Interface Simplified Schematic

POWER-DOWN INTERFACE

The quiescent and disabled currents for the AD8363 at 25°C are

approximately 60 mA and 300 μA, respectively. The dual function

pin, TCM2/PWDN, is connected to a temperature compensation

circuit as well as a power-down circuit. Typically, when PWDN

is greater than VPOS − 0.1 V, the device is fully powered down.

Figure 28 shows this characteristic as a function of VPWDN. Note

that because of the design of this section of the AD8363, as

VTCM2 passes through a narrow range at ~4.5 V (or ~VPOS − 0.5 V),

the TCM2/PWDN pin sinks approximately 750 μA. The source

used to disable the AD8363 must have a sufficiently high current

capability for this reason. Figure 23 shows the typical response

times for various RF input levels. The output reaches within 0.1 dB

of its steady-state value in approximately 35 μs; however, the refer-

ence voltage is available to full accuracy in a much shorter time.

This wake-up response varies depending on the input coupling

and the capacitances, CHPF and CLPF.

TCM2/

PWDN

COMM

VPOS

200Ω

7kΩ

VREF

INTERCEPT

TEMPERATURE

COMPENSATION

200Ω

POWER-UP

CIRCUIT

SHUTDOWN

CIRCUIT

ESD

Figure 39. PWDN Interface Simplified Schematic

VSET INTERFACE

The VSET interface has a high input impedance of 72 kΩ.

The voltage at VSET is converted to an internal current used

to set the internal VGA gain. The VGA attenuation control is

approximately 19 dB/V.

COMM

2.5kΩ

18kΩ

VSET

GAIN ADJUST

54kΩ

Figure 40. VSET Interface Simplified Schematic

OUTPUT INTERFACE

The output driver used in the AD8363 is different from the

output stage on the AD8362. The AD8363 incorporates rail-to-

rail output drivers with pull-up and pull-down capabilities. The

closed-loop −3 dB bandwidth of the VOUT buffer with no load

is approximately 58 MHz with a single-pole roll-off of −20 dB/dec.

The output noise is approximately 45 nV/√Hz at 100 kHz, which is

independent of CLPF due to the architecture of the AD8363.

VOUT can source and sink up to 10 mA. There is an internal

load between VOUT and COMM of 2.5 kΩ.

VOUT

CLPF

2kΩ

500Ω

2pF

ESD

VPOS

COMM

Figure 41. VOUT Interface Simplified Schematic

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