AD8363ACPZ-R2 datasheet(23/29 Pages) AD

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Data Sheet

AD8363

Rev. B | Page 23 of 29

Figure 51 shows the response for a 2.14 GHz pulsed signal,

with CLPF = 3900 pF. The residual ripple from a single carrier

CDMA2000 9CH SR1 signal is 150 mV p-p. (The ripple is not

shown in Figure 51. The ripple was measured separately.) Figure 52

shows the response for a 2.14 GHz pulse signal with a CLPF of

390 pF and an output filter that consists of a series 75 Ω resistor

(closest to the output) followed by a 0.15 μF capacitor to ground.

The residual ripple for this configuration is also 150 mV p-p.

Note that the rise time is faster and the fall time is slower when

the larger CLPF is used to obtain a 150 mV p-p ripple.

CH1 500mV

M 100µs

A CH1

720mV

T 10.40%

CH1 RISE

8.480µs

CH1 FALL

101.4µs

CH1 AMPL

2.37V

Figure 51. Pulse Response with CLPF = 3900 pF Resulting in a 150 mV p-p

Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz

CH1 500mV

M 100µs

A CH1

750mV

T 10.60%

CH1 RISE

13.66µs

CH1 FALL

35.32µs

CH1 AMPL

2.36V

VSET

TEMP

VOUT

CLPF

75Ω

390pF

0.15µF

OSCILLOSCOPE

PROBE

Figure 52. Pulse Response with CLPF = 390 pF and Series 75 Ω Resistor

Followed by a 0.15 μF Capacitor to Ground, Resulting in a 150 mV p-p

Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz

RF PULSE RESPONSE AND VTGT

The response of the AD8363 to pulsed RF waveforms is affected

by VTGT. Referring to Figure 21 and Figure 22, there is a period

of inactivity between the start of the RF waveform and the time

at which VOUT begins to show a reaction. This happens as a result of

the implementation of the balancing of the squarer currents within

the AD8363. This delay can be reduced by decreasing VTGT;

however, as previously noted in the VTGT Interface section,

this has implications on the sensitivity, intercept, and dynamic

range. While the delay is reduced, reducing VTGT increases the

rise and fall time of VOUT.

CONTROLLER MODE BASIC CONNECTIONS

In addition to being a measurement device, the AD8363 can

also be configured to control rms signal levels, as shown in

Figure 53.

The RF input to the device is configured as it was in measurement

mode and either input can be used. A directional coupler taps

off some of the power being generated by the VGA. If loss in the

main signal path is not a concern, and there are no issues with

reflected energy from the next stage in the signal chain, a power

splitter can be used instead of a directional coupler. Some

additional attenuation may be required to set the maximum

input signal at the AD8363 to be equal to the recommended

maximum input level for optimum linearity and temperature

stability at the frequency of operation.

The VSET and VOUT pins are no longer shorted together. VOUT

now provides a bias or gain control voltage to the VGA. The gain

control sense of the VGA must be negative and monotonic, that is,

increasing voltage tends to decrease gain. However, the gain

control transfer function of the device does not need to be well

controlled or particularly linear. If the gain control sense of the

VGA is positive, an inverting op amp circuit with a dc offset

shift can be used between the AD8363 and the VGA to keep the

gain control voltage in the 0.03 V to 4.8 V range.

VSET becomes the set-point input to the system. This can be

driven by a DAC, as shown in Figure 53, if the output power is

expected to vary, or it can simply be driven by a stable reference

voltage, if constant output power is required. This DAC should

have an output swing that covers the 0.15 V to 3.5 V range.

AD8363

CLPF

C10

C12

VSET

VOUT

DAC

(0.15V TO 3.5V)

(0.03V TO 4.8V AVAILABLE SWING)

ATTENUATOR

POUT

VAPC

VGA OR VVA

(OUTPUT POWER

DECREASES AS

VAPC INCREASES)

INHI

INLO

SEE TEXT

Figure 53. Controller Mode Operation for Automatic Power Control

When VSET is set to a particular value, the AD8363 compares

this value to the equivalent input power present at the RF input.

If these two values do not match, VOUT increases or decreases in

an effort to balance the system. The dominant pole of the error

amplifier/integrator circuit that drives VOUT is set by the capacitance

on the CLPF pin; some experimentation may be necessary to

choose the right value for this capacitor.

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