AD8363ACPZ-R2 datasheet(14/29 Pages) AD

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AD8363

Data Sheet

Rev. B | Page 14 of 29

THEORY OF OPERATION

The computational core of the AD8363 is a high performance

AGC loop. As shown in Figure 33, the AGC loop comprises a

wide bandwidth variable gain amplifier (VGA), square law

detectors, an amplitude target circuit, and an output driver. For

a more detailed description of the functional blocks, see the

AD8362 data sheet.

The nomenclature used in this data sheet to distinguish

between a pin name and the signal on that pin is as follows:



The pin name is all uppercase (for example, VPOS,

COMM, and VOUT).



The signal name or a value associated with that pin is the

pin mnemonic with a partial subscript (for example, CLPF,

CHPF, and VOUT).

SQUARE LAW DETECTOR AND AMPLITUDE TARGET

The VGA gain has the form

GSET = GO exp(−VSET/VGNS)

(1)

where:

GO is the basic fixed gain.

VGNS is a scaling voltage that defines the gain slope (the decibel

change per voltage). The gain decreases with increasing VSET.

The VGA output is

VSIG = GSET × RFIN = GO × RFIN exp(VSET/VGNS)

(2)

where RFIN is the ac voltage applied to the input terminals of the

AD8363.

The output of the VGA, VSIG, is applied to a wideband square

law detector. The detector provides the true rms response of the

RF input signal, independent of waveform. The detector output,

ISQR, is a fluctuating current with positive mean value. The

difference between ISQR and an internally generated current,

ITGT, is integrated by CF and the external capacitor attached to

the CLPF pin at the summing node. CF is an on-chip 25 pF filter

capacitor, and CLPF, the external capacitance connected to the

CLPF pin, can be used to arbitrarily increase the averaging time

while trading off with the response time. When the AGC loop is

at equilibrium

Mean(ISQR) = ITGT

(3)

This equilibrium occurs only when

Mean(VSIG2) = VTGT2

(4)

where VTGT is the voltage presented at the VTGT pin. This pin

can conveniently be connected to the VREF pin through a voltage

divider to establish a target rms voltage VATG of ~70 mV rms, when

VTGT = 1.4 V.

Because the square law detectors are electrically identical and

well matched, process and temperature dependent variations

are effectively cancelled.

TCM1

TCM2/PWDN

BAND GAP

REFERENCE

COMM

VOUT

TEMP (1.4V)

VREF (2.3V)

ISQR

ITGT

GSET

(INTERNAL)

CHPF

(EXTERNAL)

CLPF

(EXTERNAL)

(INTERNAL)

VSIG

VGA

SUMMING

NODE

VSET

CHPF

VPOS

INHI

INLO

TEMPERATURE COMPENSATION

AND BIAS

TEMPERATURE

SENSOR

VTGT

CLPF

VATG =

VTGT

Figure 33. Simplified Architecture Details

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