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Data Sheet

AD8363

time. The speed at which VSET slews can create a time varying offset

that falls within the high-pass corner set by CHPF. Therefore, in

measurement mode, take care to set CLPF appropriately to reduce

the slew. It is also worth noting that most of the typical

performance data was derived with CLPF = 3.9 nF and CHPF = 2.7 nF

and with a CW waveform.

The minimum appropriate CLPF based on slew rate limitations is

as follows

CLPF > 20 × 10−3/FREQRFIN

(18)

where:

CLPF is in farads.

FREQRFIN is in hertz.

This takes into account the on-chip 25 pF capacitor, CF, in

parallel with CLPF. However, because there are other internal

device time delays that affect loop stability, use a minimum CLPF

of 390 pF.

The minimum appropriate CHPF for a given high-pass pole

frequency is

CHPF = 29.2 × 10−6/FHPPOLE − 25 pF

(19)

where FHPPOLE is in hertz.

The subtraction of 25 pF is a result of the on-chip 25 pF

capacitor in parallel with the external CHPF. Typically, choose

CHPF to give a pole (3 dB corner) at least 1 decade below the

desired signal frequency. Note that the high pass corner of the

offset compensation system is approximately 1 MHz without an

external CHPF; therefore, adding an external capacitor lowers the

corner frequency.

The following example illustrates the proper selection of the input

coupling capacitors, minimum CLPF, and maximum CHPF when

using the AD8363 in measurement mode for a 1 GHz input signal.

1. Choose the input coupling capacitors that have a 3 dB

corner at least one decade below the input signal frequency.

From Equation 8, C > 10/(2 × π × RFIN × 50) = 32 pF

minimum. According to this calculation, 32 pF is sufficient;

however, the input coupling capacitors should be a much

larger value, typically 0.1 µF. The offset compensation

circuit, which is connected to CHPF, should be the true

determinant of the system high-pass corner frequency and

not the input coupling capacitors. With 0.1 µF coupling

capacitors, signals as low as 32 kHz can couple to the input,

which is well below the system high-pass frequency.

2. Choose CLPF to reduce instabilities due to VSET slew rate.

See Equation 18, where FRQRFIN = 1 GHz, and this results in

CLPF > 20 pF. However, as previously mentioned, values

below 390 pF are not recommended. For this reason, a 470 pF

capacitor was chosen. In addition, if fast response times are

not required, an even larger CLPF value than given here

should be chosen.

3. Choose CHPF to set a 3 dB corner to the offset compensation

system. See Equation 19, where FHPPOLE is in this case

100 MHz, one decade below the desired signal. This results

in a negative number and, obviously, a negative value is not

practical. Because the high-pass corner frequency is already

1 MHz, this result simply illustrates that the appropriate

solution is to use no external CHPF capacitor.

Note that per Equation 9

FreqLP ≈ 1.83 × ITGT/(CLPF)

A CLPF of 470 pF results in a small signal low-pass corner

frequency of approximately 144 kHz. This reflects the bandwidth

of the measurement system, and how fast the user can expect

changes on the output. It does not imply any limitations on the

input RF carrier frequency.

gm2

gm1

A = 1

40dB

g × X2

CHPF

VPOS

VGA

110Ω

25pF

(INTERNAL)

1pF

IRF

RFIN

Figure 48. Offset Compensation Circuit

CHOOSING A VALUE FOR CLPF

The Small Signal Loop Response section and the Offset

Compensation, Minimum CLPF, and Maximum CHPF

Capacitance Values section discussed how to choose the

minimum value capacitance for CLPF based on a minimum

capacitance of 390 pF, slew rate limitation, and frequency of

operation. Using the minimum value for CLPF allows the quickest

response time for pulsed type waveforms (such as WiMAX) but

also allows the most residual ripple on the output caused by the

pseudorandom modulation waveform. There is not a maximum

for the capacitance that can be applied to the CLPF pin, and in

most situations, a large enough capacitor can be added to remove

the residual ripple caused by the modulation and yet allow a fast

enough response to changes in input power.

Figure 49 shows how residual ripple, rise time, and fall time

vary with filter capacitance when the AD8363 is driven by a

single carrier CDMA2000 9CH SR1 signal at 2.14 GHz. The rise

time and fall time is based on a signal that is pulsed between no

signal and 10 dBm but is faster if the input power change is less.

Rev. B | Page 21 of 29

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