AD8363ACPZ-R2 datasheet(18/29 Pages) AD

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AD8363

Data Sheet

Rev. B | Page 18 of 29

VTGT INTERFACE

The target voltage can be set with an external source or by

connecting the VREF pin (nominally 2.3 V) to the VTGT pin

through a resistive voltage divider. With 1.4 V on the VTGT pin,

the rms voltage that must be provided by the VGA to balance the

AGC feedback loop is 1.4 V × 0.05 = 70 mV rms. Most of the

characterization information in this data sheet was collected at

VTGT = 1.4 V. Voltages higher and lower than this can be used;

however, doing so increases or decreases the gain at the internal

squaring cell, which results in a corresponding increase or

decrease in intercept. This in turn affects the sensitivity and the

usable measurement range. Because the gain of the squaring

cell varies with temperature, oscillations or a loss in measurement

range can result. For these reasons, do not reduce VTGT below 1.3 V.

VTGT

50kΩ

10kΩ

ESD

VPOS

COMM

g × X2

ITGT

Figure 42. VTGT Interface Simplified Schematic

MEASUREMENT MODE BASIC CONNECTIONS

The AD8363 requires a single supply of nominally 5 V. The

supply is connected to the two supply pins, VPOS. Decouple

the pins using two capacitors with values equal or similar to

those shown in Figure 43. These capacitors must provide a low

impedance over the full frequency range of the input, and they

should be placed as close as possible to the VPOS pins. Use two

different capacitor values in parallel to provide a broadband ac

short to ground.

Input signals can be applied differentially or single-ended; however,

in both cases, the input impedance is 50 Ω. Most performance

information in this data sheet was derived with a single-ended

drive. The optimal measurement range is achieved using a single-

ended drive on the INHI pin at frequencies below 2.6 GHz (as

shown in Figure 43), and likewise, optimal performance is

achieved using the INLO pin above 2.6 GHz (similar to Figure 43;

except INLO is ac-coupled to the input and INHI is ac-coupled

to ground).

The AD8363 is placed in measurement mode by connecting

VOUT to VSET. This closes the AGC loop within the device

with VOUT representing the VGA control voltage, which is

required to present the correct rms voltage at the input of the

internal square law detector.

TEMP

VOUT

TCM1

VREF

VPOS2

TCM2/PWDN

VPOS1

INHI

INLO

TCM1

TEMP

VSET

VOUT

CLPF

AD8363

DUT1

C12

0.1µF

C10

0.1µF

100pF

LOW FREQUENCY INPUT

0.1µF

100pF

C13

0.1µF

OPEN

PADDLE

AGND

R11

1.4kΩ

R10

845Ω

Figure 43. Measurement Mode Basic Connections

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