ADRF6518ACPZ-R7 datasheet(26/39 Pages) AD

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ADRF6518

Data Sheet

Rev. A | Page 26 of 39

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 72 shows the basic connections for a typical ADRF6518

application.

SUPPLY DECOUPLING

Apply a nominal supply voltage of 3.3 V to the supply pins,

VPS, VPI, and VPSD. The supply voltage must not exceed

3.45 V or drop below 3.15 V for VPS and VPSD. The supply

voltage on VPI must not exceed 5.25 V. Decouple each supply

pin to ground with at least one low inductance, surface-mount

ceramic capacitor of 0.1 μF placed as close as possible to the

ADRF6518 device.

The ADRF6518 has three separate supplies: two analog supplies

and a digital supply. Take care to separate the analog and digital

supplies with a large surface-mount inductor of 33 μH. Then

decouple each supply separately to its respective ground through

a 10 μF capacitor.

INPUT SIGNAL PATH

Each signal path has an input VGA, accessed through the INP1,

INM1, INP2, and INM2 pins, that sets a differential input

impedance of 400 Ω.

The inputs can be dc-coupled or ac-coupled. To ac couple the

inputs, the user must pull the VICM/AC pin to ground. This

provides an input common-mode voltage of VPI/2. To dc

couple the inputs, let the VICM pin float. If using direct dc

coupling, the common-mode voltage, VCM, can range from

1.35 V to 1.95 V while VPI = 3.3 V. The user has the option of tying

VPI to a voltage up to 5 V. This provides a common-mode range of

1.35 V to 3.1 V. In general, the minimum input common-mode

voltage is always 1.35 V, but the maximum common-mode voltage

is VCM_MAX = 0.64 × VPI − 0.135 V. The VICM pin can be used as a

reference common-mode voltage for driving a high impedance

sensing node of the preceding cascaded part (VICM has a

7.75 kΩ impedance).

OUTPUT SIGNAL PATH

The low impedance (10 Ω) output buffers are designed to drive

a high impedance load, such as an ADC input or another amplifier

stage. The output pins—OPP1, OPM1, OPP2, and OPM2—sit

at a nominal output common-mode voltage of VPS/2, but can

be driven to a voltage of 0.9 V to VPS − 1.2 V by applying the

desired common-mode voltage to the high impedance VOCM

pin.

DC OFFSET COMPENSATION LOOP ENABLED

When the dc offset compensation loop is enabled via B1 of the

SPI register, the ADRF6518 can null the output differential dc

level. The loop is enabled by setting B1 = 0. The offset

compensation loop creates a high-pass corner frequency, which

is proportional to the value of the capacitors that are connected

from the OFS1 and OFS2 pins to ground. For more information

about setting the high-pass corner frequency, see the DC Offset

Compensation Loop section.

Figure 72. Basic Connections

VPSD

COMD

CLK

DATA

SDO/RST

VICM/AC

VPI

OPP1

OPM1

COM

VGN3

VOCM

COM

OPM2

OPP2

COM

INP2

INM2

VPS

VPK

VGN2

OFS2

VPS

ENBL

INP1

INM1

VPS

RAVG

VGN1

OFS1

VPS

VPSD

0.1µF

VPI

VPS

OUTPUT1(+)

INPUT1(–)

0.1µF

INPUT1(+)

INPUT2(+)

INPUT2(–)

OUTPUT1(–)

OUTPUT2(–)

OUTPUT2(+)

0.1µF

ADRF6518

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