Data Sheet

ADRF6518

Rev. A | Page 5 of 39

TIMING DIAGRAMS

Figure 2. Write Mode Timing Diagram

Figure 3. Read Mode Timing Diagram

WRITE BIT

MSB - 2

LSB + 1

LSB

CLK

LE

DATA

LSB + 2

MSB – 1

MSB

LSB + 3

MSB – 3

MSB – 2

NOTES

1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A WRITE OPERATION,

THE FIRST BIT SHOULD BE A LOGIC 1. THE 16-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.

DC

DC

READ BIT

DC

DC

DC

DC

DC

LSB + 1

LSB

CLK

LE

DATA

SDO

LSB + 2

LSB + 3

MSB – 3

MSB – 2

MSB – 1

MSB

DC

DC

NOTES

1. THE FIRST BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A READ OPERATION, THE FIRST

BIT SHOULD BE A LOGIC 0 ON THE DATA LINE.

CLOCKED OUT ON THE CONSECUTIVE RISING EDGES OF THE CLOCK