ADRF6518ACPZ-R7 datasheet(37/39 Pages) AD

37 / 39 page

Data Sheet

ADRF6518

Rev. A | Page 37 of 39

Table 6. Evaluation Board Configuration Options

Components

Function

Default Conditions

C1, C2, C4, C11, C12, C15, C16,

C30, C31, L1, L2, R2, R3, P4

Power supply and ground decoupling. Nominal supply decoupling

consists of a 0.1 µF capacitor to ground.

C1, C2, C30 = 10 µF (Size 1210)

C4, C11, C12, C15, C16, and

C31 = 0.1 µF (Size 0402)

L1, L2 = 33 µH (Size 1812)

R2, R3 = 0 Ω (Size 0402)

P4 = installed

T1, T2, C3, C6, C7 to C10, R31,

R32, R43, R44, R45, R46, R47,

R48, R49, R50

Input interface. The INP1_SE, INM1, INP2_SE, and INM2 input SMAs

are used to drive the part differentially by bypassing the baluns.

Using only INP1_SE and INP2_SE in conjunction with the baluns

enables single-ended operation. The default configuration of the

evaluation board is for single-ended operation.

T1 and T2 are 8:1 impedance ratio baluns that transform a single-

ended signal in a 50 Ω system into a balanced differential signal in a

400 Ω system.

R31, R32, R47, R48, R49, and R50 are populated for appropriate

balun interface

To bypass the T1 and T2 baluns for differential interfacing, remove

the balun interfacing resistors, R31, R32, R47, R48, R49, and R50, and

populate R43, R44, R45, and R46 with 0 Ω resistors.

T1, T2 = Pulse Electronics

CX2049LNL

C3, C6 = 0.1 µF (Size 0402)

C7 to C10 = 0.1 µF (Size 0602)

R31, R32, R47 to R50 = 0 Ω (Size

0402)

R43 to R46 = open (Size 0402)

T3, T4, C19 to C24,

R5, R6,

R19, R20,

R35 to R42

Output interface. The OPP1, OPM1_SE, OPP2, and OPM2_SE output

SMAs are used to obtain differential signals from the part when the

output baluns are bypassed. Using OPM1_SE, OPM2_SE, and the

baluns, the user can obtain single-ended output signals. The default

configuration of the evaluation board is for single-ended operation.

T3 and T4 are 8:1 impedance ratio baluns that transform a

differential signal in a 400 Ω system into a single-ended signal in a

50 Ω system.

To bypass the T3 and T4 baluns for differential interfacing, remove

the balun interfacing resistors, R19, R20, R35, R36, R41, and R42, and

populate R37, R38, R39, and R40 with 0 Ω resistors.

R5 and R6 can be populated with an impedance of at least 400 Ω to

terminate the output in differential applications.

T3, T4 = Pulse Electronics

CX2049LNL

C19 to C24 = 0.1 µF (Size 0402)

R5, R6 = open (size 0402)

R19, R20, R35, R36, R41, R42 = 0 Ω

(Size 0402)

R37 to R40 = open

(Size 0402)

Enable interface. The ADRF6518 is powered up by applying a logic

high voltage to the ENBL pin (Jumper P2 is connected to VPS).

P2 = installed for enable

P3, R1, R17, R18, R21, R63, C25,

C53, C55, C56

Serial control interface. The digital interface sets the corner

frequency, VGA1/VGA2/VGA3 maximum gains, and the

postamplifier maximum gain using the serial interface via the LE,

CLK, DATA, and SDO pins.

RC filter networks can be populated on the CLK, LE, and DATA lines

to filter the SPI signals. CLK, DATA, and LE signals can be observed

via P3 for debug purposes. Setting C25, C53, and C56 = 330 pF is

recommending for filtering.

P3 = installed

R1 = 0 Ω (Size 0402)

R21 = 10 kΩ (Size 0402)

C25, C53, C55, C56 = open (Size

0402)

R17, R18, R63 = 1 kΩ (Size 0402)

C13, C14

DC offset compensation loop. The dc offset compensation loop is

enabled via the SPI port. When enabled, the C13 and C14 capacitors

are connected to circuit common. The high-pass corner frequency is

expressed as follows:

fHP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF))

C13, C14 = 0.1 µF (Size 0402)

Input common-mode reference. The input common-mode voltage

can be monitored at the VICM pin. If the VICM pin is left open, an

input common-mode voltage must be supplied externally ( DC

coupling mode). If VICM pin is connected to ground, the input

common-mode defaults to VPI/2 (ac coupling mode).

C5 = 0.1 µF (Size 0402)

C18

Output common-mode setpoint. The output common-mode

voltage can be set externally when applied to the VOCM pin. If the

VOCM pin is left open, the output common-mode voltage defaults

to VPS/2.

C18 = 0.1 µF (Size 0402)

C17, C27, C32

Analog gain control. The range of the analog gain pins, VGN1, VGN2,

and VGN3, is from 0 V to 1 V, creating a gain scaling of 30 mV/dB.

C17, C27, C32 = 0.1 µF (Size 0402)

P1, R4, R15, C33, C34

Peak detector.

P1 = installed

ADRF6518ACPZ-R7 数据表(PDF) 37 Page - Analog Devices

ADRF6518ACPZ-R7 数据表(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

数据表下载