ADRF6518ACPZ-R7 datasheet(22/39 Pages) AD

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ADRF6518

Data Sheet

Rev. A | Page 22 of 39

PEAK DETECTOR

To measure the signal level at the critical interface of the VGA1

output and the programmable filter input, a peak detector has

been implemented. The peak detector simultaneously measures

both channels at the VGA1 output and reports the bigger of the

two at the VPK pin. The on-chip holding capacitor and negligi-

ble leakage at the internal node ensure a large droop time of the

order of a millisecond, which is a function of the peak voltage as

well. Bigger peak voltage results in longer droop time. The droop

time can be adjusted down by placing a resistor between the

RAVG and VPS pins. Typical values of RAVG can range from

1 MΩ to 1 kΩ. As the RAVG resistor value is reduced, the peak

voltage, VPK, appears as an envelope output. The peak detector

has the attack bandwidth of 100 MHz.

The peak detector can be used in an AGC loop to set the appropri-

ate signal level at the filter input. For such an implementation,

filter VPK appropriately, considering that it is a peak hold

output. A high pulse of 25 ns or longer duration applied to the

SDO/RST dual function pin resets the VPK voltage to 0 V by

discharging the internal holding capacitor.

PROGRAMMABLE FILTERS

The integrated programmable filter is the key signal processing

function in the ADRF6518. The filters follow a six-pole Butter-

worth prototype response that provides a compromise between

band rejection, ripple, and group delay. The 0.5 dB bandwidth is

programmed from 1 MHz to 63 MHz in 1 MHz steps via the serial

programming interface (SPI) as described in the Programming

the ADRF6518 section.

The filters are designed so that the Butterworth prototype filter

shape and group delay responses vs. frequency are retained for

any bandwidth setting. Figure 69 and Figure 70 illustrate the

ideal six-pole Butterworth response. The group delay, τg, is

defined as

τg = −∂φ/∂ω

where:

φ is the phase in radians.

ω = 2πf is the frequency in radians per second.

Note that for a frequency scaled filter prototype, the absolute

magnitude of the group delay scales inversely with the band-

width; however, the shape is retained. For example, the peak

group delay for a 28 MHz bandwidth setting is 14× less than

for a 2 MHz setting.

Figure 69. Sixth-Order Butterworth Magnitude Response for 0.5 dB

Bandwidths

Figure 70. Sixth-Order Butterworth Group Delay Response for

0.5 dB Bandwidths Programmed to 2 MHz and 28 MHz

The corner frequency of the filters is defined by RC products,

which can vary by ±30% in a typical process. Therefore, all the

parts are factory calibrated for corner frequency, resulting in

a residual ±8% corner frequency variation over the −40°C to

+85°C temperature range. Although absolute accuracy requires

calibration, the matching of RC products between the pair of

channels is better than 1% by observing careful design and

layout practices. Calibration and excellent matching ensure

that the magnitude and group delay responses of both channels

track together, a critical requirement for digital IQ-based

communication systems.

Bypassing the Filters

For higher bandwidth applications, filters of the ADRF6518 can

be bypassed via the SPI. In the filter bypass mode, filters are

disabled and power consumption is significantly reduced. The

bandwidth of cascaded VGAs, which is significantly larger than

63 MHz maximum of the filters, is fully realized in the filter

bypass mode.

–20

–40

–60

–80

–100

–120

–140

–160

–180

100k

10M

100M

FREQUENCY (Hz)

1MHz

2MHz

4MHz

8MHz

16MHz

32MHz

63MHz

500

400

300

200

100

–100

100k

10M

100M

FREQUENCY (Hz)

BW = 2MHz

BW = 28MHz

14×

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