ADRF6518ACPZ-R7 datasheet(27/39 Pages) AD

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Data Sheet

ADRF6518

Rev. A | Page 27 of 39

COMMON-MODE BYPASSING

Decouple the ADRF6518 common-mode pins, VICM/AC and

VOCM, to ground. Use at least one low inductance, surface-

mount ceramic capacitor with a value of 0.1 μF to decouple the

common-mode pins.

SERIAL PORT CONNECTIONS

The ADRF6518 has a SPI port to control the gain and filter band-

width settings. Data can be written to the internal 15-bit register

and read from the register. It is recommended that low-pass RC

filtering be placed on the SPI lines to filter out any high frequency

glitches. See Figure 90, the evaluation board schematic, for an

example of a low-pass RC filter.

ENABLE/DISABLE FUNCTION

To enable the ADRF6518, pull the ENBL pin high. Driving the

ENBL pin low disables the device, reducing current consump-

tion to approximately 1 mA at room temperature. For the

disable function to work properly, connect 10 kΩ pull-down

resistors from the signal output pins (OPP1, OPM1, OPP2,

OPM2) to ground to allow a dc path to ground for proper

discharge (see Figure 67). If the disable function is not used,

pull-down resistors are not necessary.

GAIN PIN DECOUPLING

The ADRF6518 has three analog gain control pins: VGN1,

VGN2, and VGN3. Use at least one low inductance, surface-

mount ceramic capacitor with a value of 0.1 μF to decouple

each gain control pin to ground.

PEAK DETECTOR CONNECTIONS

The ADRF6518 has a peak detector output on the VPK pin,

with a scaling of 1 V/V peak differential at filter inputs. The

bigger peak of the two channels is reported. The peak detector

time-constant can be changed with a resistor from the RAVG

pin to VPS. Leave the RAVG pin open for the longest time-

constant (hold time). The RAVG resistor range is ∞ to 1 kΩ.

To reset the peak detector, pull the SDO/RST pin high for 25 ns

or longer. Logic levels are VLOW < 0.8 V, VHIGH > 2 V.

ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE

Error vector magnitude (EVM) is a measure used to quantify

the performance of a digital radio transmitter or receiver by

measuring the fidelity of the digital signal transmitted or

received. Various imperfections in the link, such as magnitude

and phase imbalance, noise, and distortion, cause the

constellation points to deviate from their ideal locations.

In general, a receiver exhibits three distinct EVM limitations

vs. received input signal power. As signal power increases, the

distortion components increase.

•

At large enough signal levels, where the distortion compo-

nents due to the harmonic nonlinearities in the device are

falling in-band, EVM degrades as signal levels increase.

•

At medium signal levels, where the signal chain behaves

in a linear manner and the signal is well above any notable

noise contributions, EVM has a tendency to reach an opti-

mal level determined dominantly by either the quadrature

accuracy and IQ gain match of the signal chain or the

precision of the test equipment.

•

As signal levels decrease, such that noise is a major con-

tributor, EVM performance vs. the signal level exhibits

a decibel-for-decibel degradation with decreasing signal

level. At these lower signal levels, where noise is the

dominant limitation, decibel EVM is directly proportional

to the SNR.

EVM TEST SETUP

The basic setup to test the EVM for the ADRF6518 consisted of

an Agilent MXG N5182B vector signal generator used as a

signal source and an Agilent DSO7104B oscilloscope used to

sample the signal while connected to a computer running Agilent

89600 vector signal analysis (VSA) software to calculate the EVM

of the signal. The I and Q outputs of the ADRF6518 were

loaded with 400 Ω differential impedances and connected

differentially to two AD8130 amplifiers to convert the signals

into single-ended signals. The single-ended signals were

connected to the input channels of the vector signal analyzer.

EVM MEASUREMENT

EVM was measured for the ADRF6518 only (the AD8130

amplifiers were used, but their EVM contribution is minimal

and do not dominate the measurement). The N5182B IQ baseband

differential outputs drove the ADRF6518 inputs through 1 µF

coupling capacitors. Large coupling capacitors are necessary to

keep the high-pass corner created by the capacitors as low as

possible and to prevent the low-pass corner from corrupting the

signal. The VICM/AC pin was grounded to enable ac coupling.

The VPI pin was connected to 3.3 V by shorting it to VPS. The

alpha of the pulse response filter was set to 0.35. The baseband

input power to the ADRF6518 was swept, and the analog gains

were adjusted to maintain a target 1.5 V p-p differential signal

level on both the I and Q outputs. The VGA1 analog gain was

adjusted to limit its output to 1.5 V p-p (0.75 V peak on the

peak detector output). The filter corner was set to 63 MHz, and

the digital gains for VGA1, VGA2, VGA3, and the postamplifier

were set to 15 dB, 21 dB, 21 dB, and 3 dB, respectively. Several

signal bandwidths, signal types, gains, and output levels were

tested, in filter mode and in filter bypass mode.

It is important to keep the high-pass corner of the output offset

compensation loop low compared to the signal bandwidth. The

lower the signal bandwidth is, the lower the user must set the

high-pass corner to ensure that the minimal amount of the

signal is not corrupted. See the Applications Information

section of the ADRF6510 and the ADRF6516 data sheets for

additional information on the effects of setting the high-pass

corner too high in frequency.

It is also important to set the filter corner appropriately for the

given signal bandwidth. The user must be careful not to set the

filter corner too low in an attempt to achieve more rejection of

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