ADRF6518ACPZ-R7 datasheet(23/39 Pages) AD

23 / 39 page

Data Sheet

ADRF6518

Rev. A | Page 23 of 39

VARIABLE GAIN AMPLIFIERS (VGAs)

The cascaded VGA2 and VGA3 are also based on the X-AMP

architecture, and each has 24 dB gain range with separate high

impedance gain control inputs, VGN2 and VGN3. The VGA

structures of the second and third VGAs are identical to that of

the first VGA. However, these have slightly higher noise figure

and less drive level capability. Their output is rated at 1 V p-p

for >60 dBc HD2 and HD3. Depending on the input signal

range, the second or third VGA or both can be used for AGC

purposes. The critical level to consider while making this choice

is the signal level at the output of the VGAs, which must not

exceeded 1 V p-p to maintain low distortion.

The fixed gain following both of the variable gain sections can

also be programmed to 12 dB, 15 dB, 18 dB, or 21 dB to maxim-

ize the dynamic range.

OUTPUT BUFFERS/ADC DRIVERS

The low impedance (<10 Ω) output buffers of the ADRF6518

are designed to drive either ADC inputs or subsequent amplifier

stages. They are capable of delivering up to 4 V p-p composite

two-tone signals into 400 Ω differential loads with >60 dBc

IMD3. The output common-mode voltage defaults to VPS/2,

but it can be adjusted from 900 mV to VPS − 1.2 V without loss

of drive capability by presenting the VOCM pin with the

desired common-mode voltage. The high input impedance of

VOCM allows the ADC reference output to be connected

directly. Even though the output common-mode voltage is

adjustable, and the offset compensation loop can null the

accumulated dc offsets (see the DC Offset Compensation Loop

section), it may still be desirable to ac-couple the outputs by

selecting the coupling capacitors according to the load imped-

ance and desired bandwidth.

DC OFFSET COMPENSATION LOOP

In many signal processing applications, no information is

carried in the dc level. In fact, dc voltages and other low

frequency disturbances can often dominate the intended signal

and consume precious dynamic range in the analog path and

bits in the data converters. These dc voltages can be present

with the desired input signal or can be generated inside the

signal path by inherent dc offsets or other unintended signal-

dependent processes such as self-mixing or rectification.

Because the ADRF6518 is fully dc-coupled, it may be necessary

to remove these offsets to realize the maximum signal-to-noise

ratio (SNR). The external offsets can be eliminated with ac-

coupling capacitors at the input pins; however, that requires

large value capacitors because the impedances can be fairly low,

and high-pass corners may need to be <10 Hz in some cases. To

address the issue of dc offsets, the ADRF6518 provides an offset

correction loop that nulls the output differential dc level, as

shown in Figure 71. If the correction loop is not required, it can

be disabled through the SPI port.

Figure 71. Offset Compensation Loop Operates Around the VGA

and Output Buffer

The offset control loop creates a high-pass corner, fHP, that

is superimposed on the normal Butterworth filter response

when filters are enabled. Typically, fHP is many orders of

magnitude lower than the lower programmed filter bandwidth

so that there is no interaction between them. Setting fHP is

accomplished with capacitors, COFS, from the OFS1 and OFS2

pins to ground. Because the correction loop works around the

VGA sections, fHP is also dependent on the total gain of the

cascaded VGAs. In general, the expression for fHP is given by

fHP (Hz) = 6.7 × Post Filter Linear Gain/COFS (μF)

where Post Filter Linear Gain is expressed in linear terms, not

in decibels (dB), and is the gain following the filters, which

excludes the VGA1 gain.

Note that fHP increases in proportion to the gain. For this

reason, choose COFS at the highest operating gain to guarantee

that fHP is always below the maximum limit required by the

system.

PROGRAMMING THE ADRF6518

The 0.5 dB corner frequencies for both filters, the digital gains of all

the VGAs, and the output buffers are programmed simultane-

ously through the SPI port. In addition to these, enabling the dc

offset compensation loop and power mode selection are also

controlled through SPI port. A 16-bit register stores 15 data bits,

including the 6-bit code for corner frequencies of 1 MHz through

63 MHz and filter bypass, as well as the codes for VGA gains,

and the postamplifier gain (see Table 5). The SPI protocol not

only allows these selections to be written to the DATA pin, but

also allows the stored code to be read back via the SDO/RST pin.

The latch enable (LE) pin must first go to a Logic 0 for a read or

write cycle to begin. On the next rising edge of the clock (CLK),

a Logic 1 on the DATA pin initiates a write cycle, whereas a

Logic 0 on the DATA pin initiates a read cycle. In a write cycle,

the next 15 CLK rising edges latch the desired 15-bit code, LSB

first. This results in 16-bit code, including the first Logic 1 to

initiate a write cycle. When LE goes high, the write cycle is

completed and different codes are presented various blocks that

need programming. In a read cycle, the next 15 CLK falling

edges present the stored 15-bit code, LSB first. When LE goes

high, the read cycle is completed. Detailed timing diagrams are

shown in Figure 2 and Figure 3.

GAIN

FROM

FILTERS

COFS

OFSx

OFDS

50dB

VGA

OUTPUT ADC

DRIVER

BASEBAND

OUTPUTS

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