AD5424 datasheet(4/24 Pages) AD

4 / 24 page

REV. 0

–4–

AD5424/AD5433/AD5445

DATA VALID

DATA

DATA VALID

Figure 1. Timing Diagram

TIMING CHARACTERISTICS1, 2

Parameter

VDD = 2.5 V to 5.5 V

VDD = 4.5 V to 5.5 V

Unit

Conditions/Comments

ns min

W to CS setup time

ns min

W to CS hold time

ns min

CS low time (write cycle)

ns min

Data setup time

ns min

Data hold time

ns min

W high to CS low

ns min

CS min high time

ns typ

Data access time

ns max

ns typ

Bus relinquish time

ns max

NOTES

1See Figure 1. Temperature range is as follows: Y version: –40 C to +125 C. Guaranteed by design and characterization, not subject to production test.

2All input signals are specified with tr = tf = 1 ns (10% to 90% of V

DD) and timed from a voltage level of (V IL + VIH)/2. Digital output timing measured with load

circuit in Figure 2.

Specifications subject to change without notice.

(VREF = 5 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.)

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