REV. 0

AD5424/AD5433/AD5445

–19–

DAC leakage current is also a potential error source in divider

circuits. The leakage current must be counterbalanced by an

opposite current supplied from the op amp through the DAC.

as follows:

Output Error Voltage Due to DAC Leakage = (Leakage

R)/D

leakage current of 10 nA, R = 10 k

Ω and a gain (i.e., 1/D) of 16

the error voltage is 1.6 mV.

REFERENCE SELECTION

When selecting a reference for use with the AD5424 series of

current output DACs, pay attention to the references output

voltage temperature coefficient specification. This parameter not

only affects the full-scale error, but can also affect the linearity

(INL and DNL) performance. The reference temperature coeffi-

cient should be consistent with the system accuracy specifications.

For example, an 8-bit system required to hold its overall specifi-

cation to within 1 LSB over the temperature range 0 C to 50 C

dictates that the maximum system drift with temperature should

be less than 78 ppm/ C. A 12-bit system with the same tempera-

ture range to overall specification within 2 LSBs requires a

maximum drift of 10 ppm/ C. By choosing a precision reference

with low output temperature coefficient this error source can be

minimized. Table III suggests some references available from

Analog Devices that are suitable for use with this range of cur-

rent output DACs.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an

amplifier with low input bias currents and low input offset voltage.

The input offset voltage of an op amp is multiplied by the vari-

able gain (due to the code dependent output resistance of the

DAC) of the circuit. A change in this noise gain between two

adjacent digital fractions produces a step change in the output

voltage due to the amplifier’s input offset voltage. This output

voltage change is superimposed on the desired change in output

between the two codes and gives rise to a differential linearity error,

which if large enough, could cause the DAC to be nonmonotonic.

In general, the input offset voltage should be <1/4 LSB to ensure

monotonic behavior when stepping through codes.

The input bias current of an op amp also generates an offset at

the voltage output as a result of the bias current flowing in the

feedback resistor RFB. Most op amps have input bias currents

low enough to prevent any significant errors in 12-bit applications.

Common-mode rejection of the op amp is important in voltage

switching circuits since it produces a code dependent error at the

voltage output of the circuit. Most op amps have adequate common

mode rejection for use at 8-, 10-, and 12-bit resolution.

Provided the DAC switches are driven from true wideband

Consequently, the slew rate and settling time of a voltage switching

DAC circuit is determined largely by the output op amp. To

obtain minimum settling time in this configuration, it is important

in this application) of the DAC. This is done by using low

inputs capacitance buffer amplifiers and careful board design.

Most single-supply circuits include ground as part of the analog

signal range, which in turns requires an amplifier that can handle

rail-to-rail signals; there is a large range of single-supply amplifiers

available from Analog Devices.

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5424/AD5433/AD5445 is mounted should be designed so

that the analog and digital sections are separated, and confined

to certain areas of the board. If the DAC is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close as possible to the device.

These DACs should have ample supply bypassing of 10 F in

parallel with 0.1 F on the supply located as close to the package

as possible, ideally right up against the device. The 0.1 F capaci-

tor should have low effective series resistance (ESR) and effective

series inductance (ESI), like the common ceramic types that

provide a low impedance path to ground at high frequencies, to

handle transient currents due to internal logic switching. Low

ESR 1

F to 10

F tantalum or electrolytic capacitors should

also be applied at the supplies to minimize transient disturbance

and filter out low frequency ripple.

Fast switching signals such as clocks should be shielded with

digital ground to avoid radiating noise to other parts of the board,

and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A micros-

trip technique is by far the best, but not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground plane, while signal traces are

placed on the solder side.

It is good practice to employ compact, minimum lead length

PCB layout design. Leads to the input should be as short as

possible to minimize IR drops and stray inductance.

matched to minimize gain error. To maximize on high frequency

performance, the I-to-V amplifier should be located as close to

the device as possible.

EVALUATION BOARD FOR THE AD5424/AD5433/AD5445

The board consists of a 12-bit AD5445 and a current to voltage

amplifier AD8065. Included on the evaluation board is a 10 V

reference ADR01. An external reference may also be applied via

an SMB input.

The evaluation kit consists of a CD-ROM with self-installing

PC software to control the DAC. The software simply allows

the user to write a code to the device.

OPERATING THE EVALUATION BOARD

Power Supplies

The board requires

Both supplies are decoupled to their respective ground plane

with 10

F tantalum and 0.1

F ceramic capacitors.

Link1 (LK1) is provided to allow selection between the on-board

reference (ADR01) or an external reference applied through J2.