AD5424 datasheet(17/24 Pages) AD

17 / 24 page

REV. 0

AD5424/AD5433/AD5445

–17–

SINGLE-SUPPLY APPLICATIONS

Current Mode Operation

Figure 6 shows a typical circuit for operation with a single 2.5 V to

5 V supply. In the current mode circuit of Figure 6, IOUT2 and

hence IOUT1 is biased positive by the amount applied to VBIAS. In

this configuration, the output voltage is given by

OUT

DAC

BIAS

=×

()×−

()

{}+

As D varies from 0 to 255 (AD5424), 1023 (AD5433), or

4095 (AD5445), the output voltage varies from VOUT = VBIAS

to VOUT = 2 VBIAS – VIN.

VBIAS should be a low impedance source capable of sinking and

sourcing all possible variations in current at the IOUT2 terminal.

VOUT

GND

VIN

IOUT2

IOUT1

RFB

VDD

VREF

VBIAS

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

VDD

DAC

Figure 6. Single-Supply Current Mode Operation

Voltage Switching Mode of Operation

Figure 7 shows these DACs operating in the voltage-switching

mode. The reference voltage, VIN, is applied to the IOUT1 pin;

IOUT2 is connected to AGND; and the output voltage is avail-

able at the VREF terminal. In this configuration, a positive

reference voltage results in a positive output voltage making

single-supply operation possible. The output from the DAC is

voltage at a constant impedance (the DAC ladder resistance),

thus an op amp is necessary to buffer the output voltage. The

reference input no longer sees a constant input impedance, but

one that varies with code. So, the voltage input should be driven

from a low impedance source.

It is important to note that VIN is limited to low voltages be-

cause the switches in the DAC ladder no longer have the same

source-drain drive voltage. As a result, their on resistance dif-

fers, which degrades the linearity of the DAC. See TPCs 10–15.

Also, VIN must not go negative by more than 0.3 V or an inter-

nal diode will turn on, exceeding the max ratings of the device.

In this type of application, the full range of multiplying capabil-

ity of the DAC is lost.

VOUT

VDD

GND

VIN

IOUT2

IOUT1

RFB

VDD

VREF

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

DAC

Figure 7. Single-Supply Voltage Switching Mode Operation

POSITIVE OUTPUT VOLTAGE

Note that the output voltage polarity is opposite to the VREF

polarity for dc reference voltages. In order to achieve a positive

voltage output, an applied negative reference to the input of the

DAC is preferred over the output inversion through an inverting

amplifier because of the resistor tolerance errors. To generate a

negative reference, the reference can be level shifted by an op

amp such that the VOUT and GND pins of the reference become

the virtual ground and –2.5 V respectively, as shown in Figure 8.

VOUT =

0 TO +2.5V

VDD = 5V

GND

IOUT2

IOUT1

RFB

VDD

VREF

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

GND

VIN

VOUT

ADR03

+5V

–5V

1/2 AD8552

–2.5V

8-/10-/12-BIT DAC

Figure 8. Positive Voltage Output with Minimum

of Components

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