REV. 0

AD5424/AD5433/AD5445

–15–

DAC SECTION

The AD5424, AD5433, and AD5445 are 8-, 10- and 12-bit

current output DACs consisting of a standard inverting R-2R

ladder configuration. A simplified diagram for the 8-bit AD5424

value of R. The value of R is typically 10 k

Ω (minimum 8 kΩ

and maximum 12 k

potential, a constant current flows in each ladder leg, regardless

of digital input code. Therefore, the input resistance presented

resistances and capacitances. External amplifier choice should

take into account the variation in impedance generated by the

DAC on the amplifiers inverting input node.

DAC DATA LATCHES

AND DRIVERS

2R

S1

2R

S2

2R

S3

2R

S8

2R

R

R

R

R

Figure 3. Simplified Ladder

of the DAC, making the device extremely versatile and allowing it

to be configured in several different operating modes, for example,

to provide a unipolar output, 4-quadrant multiplication in bipo-

lar mode or in single-supply modes of operation. Note that a

PARALLEL INTERFACE

Data is loaded to the AD5424/33/45 in the format of an 8-, 10-, or

12-bit parallel word. Control lines

CS and R/W allow data to be

written to or read from the DAC register. A write event takes place

when

CS and R/W are brought low, data available on the data

lines fills the shift register, and the rising edge of

CS latches the

data and transfers the latched data-word to the DAC register.

The DAC latches are not transparent, thus a write sequence must

consist of a falling and rising edge on

CS to ensure data is loaded

to the DAC register and its analog equivalent reflected on the

DAC output.

A read event takes place when R/

W is held high and CS is brought

low. Now data is loaded from the DAC register back to the input

register and out onto the data line where it can be read back to

the controller for verification or diagnostic purposes.

CIRCUIT OPERATION

Unipolar Mode

Using a single op amp, these devices can easily be configured to

provide 2-quadrant multiplying operation or a unipolar output

voltage swing as shown in Figure 4.

GND

AGND

AD5424/

AD5433/AD5445

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

R1

R2

A1

C1

CS

R/

W

DATA

INPUTS

Figure 4. Unipolar Operation

When an output amplifier is connected in unipolar mode, the

output voltage is given by

VV

OUT

REF

=×

–

D

n

2

where D is the fractional representation of the digital word loaded

to the DAC and n is the resolution of the DAC.

D= 0 to 255 (8-Bit AD5424)

= 0 to 1023 (10-Bit AD5433)

= 0 to 4095 (12-Bit AD5445)

polarity for dc reference voltages.

These DACs are designed to operate with either negative or

by the internal digital logic to drive the DAC switches’ on

and off states.

These DACs are also designed to accommodate ac reference

input signals in the range of –10 V to +10 V.

With a fixed 10 V reference, the circuit shown in Figure 4 will

an ac signal, the circuit performs 2-quadrant multiplication.

Table I shows the relationship between digital code and expected

output voltage for unipolar operation. (AD5424, 8-bit device).

Table I. Unipolar Code Table

Digital Input

Analog Output (V)

1111 1111

1000 0000

0000 0001

0000 0000