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AD5424 数据表(PDF) 16 Page - Analog Devices |
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AD5424 数据表(HTML) 16 Page - Analog Devices |
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16 / 24 page ![]() REV. 0 –16– AD5424/AD5433/AD5445 VOUT = –VREF TO +VREF GND VREF 10V IOUT2 IOUT1 VDD VREF NOTES 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0 V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. AGND R3 10k AD5424/ AD5433/AD5445 R5 20k R4 10k A2 R1 VDD RFB R2 C1 CS R/ W DATA INPUTS A1 Figure 5. Bipolar Operation (4-Quadrant Multiplication) Bipolar Operation In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors as shown in Figure 5. In this circuit, the second amplifier A2 provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = –VREF) to midscale (VOUT = 0 V ) to full scale (VOUT = +VREF). VV D V OUT REF n REF =× ()− − 2 1 where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. D= 0 to 255 (8-Bit AD5424) = 0 to 1023 (10-Bit AD5433) = 0 to 4095 (12-Bit AD5445) When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table II shows the relationship between digital code and the expected output voltage for bipolar operation (AD5426, 8-bit device). Table II. Bipolar Code Table Digital Input Analog Output (V) 1111 1111 +VREF (127/128) 1000 0000 0 0000 0001 –VREF (127/128) 0000 0000 –VREF (128/128) Stability In the I-to-V configuration, the IOUT of the DAC and the invert- ing node of the op amp must be connected as close as possible, and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capaci- tance introduces a pole into the open-loop response, which can cause ringing or instability in closed-loop applications. An optional compensation capacitor, C1, can be added in parallel with RFB for stability as shown in Figures 4 and 5. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically but 1 pF to 2 pF is generally adequate for compensation. |
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