REV. 0

ADE7756

–5–

Parameter

A, B Versions

Unit

Test Conditions/Comments

Write Timing

20

ns (min)

CS falling edge to first SCLK falling edge.

150

ns (min)

SCLK logic high pulsewidth.

150

ns (min)

SCLK logic low pulsewidth.

10

ns (min)

Valid Data Setup time before falling edge of SCLK.

5

ns (min)

Data Hold time after SCLK falling edge.

6.4

µs (min)

Minimum time between the end of data byte transfers.

4

µs (min)

Minimum time between byte transfers during a serial write.

100

ns (min)

CS Hold time after SCLK falling edge.

Read Timing

4

µs (min)

Minimum time between read command (i.e., a write to Communication

Register) and data read.

4

µs (min)

Minimum time between data byte transfers during a multibyte read.

3

30

ns (min)

Data access time after SCLK rising edge following a write to the

Communications Register.

4

100

ns (max)

Bus relinquish time after falling edge of SCLK.

10

ns (min)

4

100

ns (max)

Bus relinquish time after rising edge of

CS.

10

ns (min)

NOTES

90%) and timed from a voltage level of 1.6 V.

number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics

is the true bus relinquish time of the part and is independent of the bus loading.

Specifications subject to change without notice.

200 A

1.6mA

50pF

TO

OUTPUT

PIN

2.1V

Figure 1. Load Circuit for Timing Specifications

CS

SCLK

DIN

A4

A3

A2

A1

A0

DB7

MOST SIGNIFICANT BYTE

1

DB0

DB7

DB0

LEAST SIGNIFICANT BYTE

00

COMMAND BYTE

Figure 2. Serial Write Timing

CS

SCLK

DIN

A4

A3

A2

A1

A0

00

0

DOUT

DB7

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

COMMAND BYTE

DB0

DB7

DB0

Figure 3. Serial Read Timing

5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz