ADE7756 datasheet(13/32 Pages) AD

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REV. 0

ADE7756

–13–

The contents of the Offset Correction registers are 6-bit, sign

and magnitude coded. The weighting of the LSB size depends

on the gain setting, i.e., 1, 2, 4, 8, or 16. Table II below shows

the correctable offset span for each of the gain settings and the

LSB weight (mV) for the Offset Correction registers. The

maximum value that can be written to the Offset Correction

registers is

±31 decimal—see Figure 7.

Table II. Offset Correction Range

Gain

Correctable Span

LSB Size

±60 mV

1.88 mV/LSB

±40 mV

1.25 mV/LSB

±25 mV

0.78 mV/LSB

±23 mV

0.72 mV/LSB

±20 mV

0.63 mV/LSB

Figure 7 shows the relationship between the Offset Correction

gain setting of one. In order to perform an offset adjustment, The

analog inputs should be first connected to AGND. There should

be no signal on either Channel 1 or Channel 2. A read from

Channel 1 or Channel 2 using the waveform register will give an

indication of the offset in the channel. This offset can be canceled

by writing an equal and opposite offset value to the relevant offset

another read. Note when adjusting the offset of Channel 1, one

needs to ensure the HPF has been disabled in the Mode Register.

CH1OS[7:0]

00h

1Fh

3Fh

+60mV

–60mV

0mV

OFFSET ADJUST

00 11, 1111B

SIGN + 5 BITS

00 01, 1111B

Figure 7. Channel Offset Correction Range (Gain = 1)

ZERO CROSSING DETECTION

The ADE7756 has a zero crossing detection circuit on Channel

2. This zero crossing is used to produce an external zero cross

signal (ZX) and it is also used in the calibration mode—see

Energy Calibration section. The zero crossing signal is also used

to initiate a temperature measurement on the ADE7756—see

Temperature Measurement section.

Figure 8 shows how the zero cross signal is generated from the

output of LPF1.

LPF1

21.04 @ 60Hz

0.93

1.0

V2P

V2N

ADC 2

x1, x2, x4,

x8, x16

REFERENCE

GAIN[7:5]

MULTIPLIER

–63% TO +63% FS

LPF1

f–3dB = 156Hz

ZERO

CROSS

PGA2

Figure 8. Zero Cross Detection on Channel 2

The ZX signal will go logic high on a positive going zero crossing

and logic low on a negative going zero crossing on Channel 2.

The zero crossing signal ZX is generated from the output of LPF1.

LPF1 has a single pole at 156 Hz (at CLKIN = 3.579545 MHz).

As a result there will be a phase lag between the analog input

signal V2 and the output of LPF1. The phase response of this

filter is shown in the Channel 2 Sampling section of this data

sheet. The phase lag response of LPF1 results in a time delay of

approximately 0.97 ms (@ 60 Hz) between the zero crossing on

the analog inputs of Channel 2 and the rising or falling edge of ZX.

The zero crossing detection also has an associated time-out

mented (1 LSB) every 128/CLKIN seconds. The register is

reset to its user-programmed full-scale value every time a zero

crossing on Channel 2 is detected. The default power-on value

in this register is FFFh. If the register decrements to zero before

a zero crossing is detected, and the DISSAG bit in the Mode

SAG pin will go active low. The absence of

a zero crossing is also indicated on the

IRQ output if the SAG

enable bit in the Interrupt Enable register is set to Logic 1.

Irrespective of the enable bit setting, the SAG flag in the Inter-

rupt Status register is always set when the ZXTOUT register is

decremented to zero—see ADE7756 Interrupts section.

The Zero-Cross Time-Out register can be written/read by the

user and has an address of 0Eh—see Serial Interface section.

The resolution of the register is 128/CLKIN seconds per LSB.

Thus the maximum delay for an interrupt is 0.15 second (128/

CLKIN

× 212).

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