ADE7756 datasheet(16/32 Pages) AD

16 / 32 page

REV. 0

ADE7756

–16–

TEMPERATURE MEASUREMENT

ADE7756 also includes an on-chip temperature sensor. A tem-

perature measurement can be made by setting Bit 5 in the Mode

ADE7756 will initiate a temperature measurement on the next

zero crossing. When the zero crossing on Channel 2 is detected,

the voltage output from the temperature sensing circuit is con-

nected to ADC1 (Channel 1) for digitizing. The resultant code

is processed and placed in the Temperature register (TEMP[7:0])

approximately 26

µs later (24 CLKIN cycles). If enabled in the

Interrupt Enable register (Bit 5), the

IRQ output will go active

low when the temperature conversion is finished. Please note

that temperature conversion will introduce a small amount of

noise in the energy calculation. If temperature conversion is

performed frequently (e.g., multiple times per second), a

noticeable error will accumulate in the resulting energy calcu-

lation over time.

The contents of the Temperature register are signed (two’s

complement) with a resolution of approximately 1 LSB/

°C. The

temperature register will produce a code of 00h when the ambi-

ent temperature is approximately 70

°C—see Figure 13. The

temperature measurement is uncalibrated in the ADE7756 and

has an offset tolerance that could be as high as

±20°C.

TEMPERATURE– C

–60

–120

–20

100

120

–40

–110

–80

–60

–40

–20

FIVE PARTS

APGAIN = 00h

Figure 13. Temperature Register

ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7756 is carried out

using two second-order sigma-delta ADCs. The block diagram

in Figure 14 shows a first-order (for simplicity) sigma-delta

ADC. The converter is made up of two parts, first the sigma-

delta modulator and second the digital low-pass filter.

A sigma-delta modulator converts the input signal into a con-

tinuous serial stream of 1s and 0s at a rate determined by the

sampling clock. In the ADE7756 the sampling clock is equal to

CLKIN/4. The 1-bit DAC in the feedback loop is driven by the

serial data stream. The DAC output is subtracted from the input

signal. If the loop gain is high enough, the average value of the

DAC output (and therefore the bit stream) will approach that of

the input signal level. For any given input value in a single

sampling interval, the data from the 1-bit ADC is virtually mean-

ingless. Only when a large number of samples are averaged, will

a meaningful result be obtained. This averaging is carried out in

the second part of the ADC, the digital low-pass filter. By aver-

aging a large number of bits from the modulator the low-pass

filter can produce 20-bit data words that are proportional to the

input signal level.

The sigma-delta converter uses two techniques to achieve high

resolution from what is essentially a 1-bit conversion technique.

The first is oversampling. By oversampling we mean that the

signal is sampled at a rate (frequency) that is many times higher

than the bandwidth of interest. For example, the sampling rate

in the ADE7756 is CLKIN/4 (894 kHz) and the band of interest

is 40 Hz to 2 kHz. Oversampling has the effect of spreading

the quantization noise (noise due to sampling) over a wider

bandwidth. With the noise spread more thinly over a wider

bandwidth, the quantization noise in the band of interest is

lowered—see Figure 15. However oversampling alone is not an

efficient enough method to improve the signal to noise ratio

(SNR) in the band of interest. For example, an oversampling

ratio of 4 is required just to increase the SNR by only 6 dB

(1 bit). To keep the oversampling ratio at a reasonable level, it is

possible to shape the quantization noise so that the majority of

the noise lies at the higher frequencies. This is what happens in

the sigma-delta modulator, the noise is shaped by the integrator

which has a high-pass-type response for the quantization noise.

The result is that most of the noise is at the higher frequencies

where it can be removed by the digital low-pass filter. This noise

shaping is also shown in Figure 15.

VREF

10100101

DIGITAL LOW-

PASS FILTER

MCLK/4

INTEGRATOR

1-BIT DAC

LATCHED

COMPARATOR

ANALOG LOW-

PASS FILTER

Figure 14. First Order Sigma-Delta (

Σ-∆) ADC

SIGNAL

FREQUENCY – kHz

447

894

SAMPLING

FREQUENCY

SHAPED

NOISE

ANTIALIAS

FILTER (RC)

DIGITAL

FILTER

NOISE

SIGNAL

447

894

HIGH RESOLUTION

OUTPUT FROM

DIGITAL LPF

NOISE

FREQUENCY – kHz

Figure 15. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

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