ADE7756 datasheet(26/32 Pages) AD

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ADE7756

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SUSPENDING THE ADE7756 FUNCTIONALITY

The analog and the digital circuit can be suspended separately.

The analog portion of the ADE7756 can be suspended by set-

ting the ASUSPEND bit (Bit 4) of the Mode register to logic

high—see Mode Register section. In suspend mode, all wave-

form samples from the ADCs will be set to zeros. The digital

circuitry can be halted by holding the CLKIN input to 0 or 1.

The ADE7756 can be reactivated by restoring the CLKIN input

and setting the ASUSPEND bit to logic low.

SERIAL INTERFACE

All ADE7756 functionality is accessible via several on-chip

registers—see Figure 36. The contents of these registers can be

updated or read using the on-chip serial interface. After power-

on, or toggling the

RESET pin low, on a falling edge on CS, the

ADE7756 is placed in Communications Mode. In Communications

Mode the ADE7756 expects a write to its Communications

mines whether the next data transfer operation will be a read or

a write and also which register is accessed. Therefore all data trans-

fer operations with the ADE7756, whether a read or a write,

must begin with a write to the Communications register.

COMMUNICATIONS REGISTER

ADDRESS

DECODE

OUT

DIN

DOUT

Figure 36. Addressing ADE7756 Registers via the

Communications Register

The Communications register is an 8-bit-wide register. The

MSB determines whether the next data transfer operation is a

read or a write. The 5 LSBs contain the address of the register

to be accessed. See Communications Register section for a more

detailed description.

Figure 37a and 37b show the data transfer sequences for a read

and write operation respectively.

On completion of a data transfer (read or write) the ADE7756

once again enters Communications Mode.

COMMUNICATIONS REGISTER WRITE

00 ADDRESS

DIN

DOUT

SCLK

MULTIBYTE READ DATA

Figure 37a. Data from the ADE7756 via the Serial

Interface

COMMUNICATIONS REGISTER WRITE

00 ADDRESS

DIN

SCLK

MULTIBYTE WRITE DATA

Figure 37b. Writing Data to the ADE7756 via the Serial

Interface

A data transfer is complete when the LSB of the ADE7756

or from the ADE7756.

The Serial Interface of the ADE7756 is made up of four signals

SCLK, DIN, DOUT, and

CS. The serial clock for a data trans-

fer is applied at the SCLK logic input. This logic input has a

Schmitt-trigger input structure, which allows slow rising (and

falling) clock edges to be used. All data transfer operations are

synchronized to the serial clock. Data is shifted into the ADE7756

at the DIN logic input on the falling edge of SCLK. Data is shifted

out of the ADE7756 at the DOUT logic output on a rising edge

of SCLK. The

CS logic input is the chip select input. This input

is used when multiple devices share the serial bus. A falling edge

CS also resets the serial interface and places the ADE7756 in

Communications Mode. The

CS input should be driven low for

the entire data transfer operation. Bringing

CS high during a data

transfer operation will abort the transfer and place the serial bus

in a high impedance state. The

CS logic input may be tied low if

the ADE7756 is the only device on the serial bus. However,

with

CS tied low all initiated data transfer operations must be

fully completed, i.e., the LSB of each register must be trans-

ferred as there is no other way of bringing the ADE7756 back

into Communications Mode without resetting the entire device,

i.e., using

RESET.

Serial Write Operation

The serial write sequence takes place as follows. With the

ADE7756 in Communications Mode (i.e., the

CS input logic

low), a write to the Communications register first takes place.

The MSB of this byte transfer is a 1, indicating that the data

transfer operation is a write. The LSBs of this byte contain the

address of the register to be written to. The ADE7756 starts

shifting in the register data on the next falling edge of SCLK.

All remaining bits of register data are shifted in on the falling

edge of subsequent SCLK pulses—see Figure 38.

As explained earlier, the data write is initiated by a write to the

communications register followed by the data. During a data

write operation to the ADE7756, data is transferred to all on-

chip registers one byte at a time. After a byte is transferred into

the serial port, there is a finite time before it is transferred to

one of the ADE7756 on-chip registers. Although another byte

transfer to the serial port can start while the previous byte is

being transferred to an on-chip register, this second byte trans-

fer should not finish until at least 4

µs after the end of the previous

byte transfer. This functionality is expressed in the timing speci-

fication t6—see Figure 38. If a write operation is aborted during

a byte transfer (

CS brought high), that byte will not be written

to the destination register.

Destination registers may be up to 2 bytes wide—see Register

Descriptions section. Hence the first byte shifted into the serial

port at DIN is transferred to the MSB (Most Significant Byte)

of the destination register. If the addressed register is 12 bits

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