REV. 0

ADE7756

–30–

Mode Register (06H)

The ADE7756 functionality is configured by writing to the MODE register. Table VI summarizes the functionality of each bit in the

MODE register.

Table VI. Mode Register

Bit

Bit

Location

Mnemonic

Description

0

DISHPF

The HFP (High-Pass Filter) in Channel 1 is disabled when this bit is set.

1

DISLPF2

The LPF (Low-Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.

2

DISCF

The frequency output CF is disabled when this bit is set.

3

DISSAG

The line voltage Sag detection is disabled when this bit is set.

4

ASUSPEND

By setting this bit to Logic 1, both ADE7756’s A/D converters can be turned off. In normal

operation, this bit should be left at Logic 0. All digital functionality can be stopped by sus-

pending the clock signal at CLKIN pin.

5

TEMPSEL

The temperature conversion starts when this bit is set to one. This bit is automatically reset to

zero when the temperature conversion is finished.

6

SWRST

Software Chip Reset. A data transfer should not take place to the ADE7756 for at least 18

µs

after a software reset.

7

CMODE

Setting this bit to a Logic 1 places the chip in calibration mode.

8

DISCH1

ADC 1 (Channel 1) inputs are internally shorted together.

9

DISCH2

ADC 2 (Channel 2) inputs are internally shorted together.

10

SWAP

By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the

analog inputs V1P and V1N are connected to ADC 2.

12, 11

DTRT1, 0

These bits are used to select the Waveform Register update rate.

DTRT 1

DTRT0

Update Rate

0

0

27.9 kSPS (CLKIN/128)

0

1

14 kSPS (CLKIN/256)

1

0

7 kSPS (CLKIN/512)

1

1

3.5 kSPS (CLKIN/1024)

14, 13

WAVSEL1, 0

These bits are used to select the source of the sampled data for the Waveform Register

WAVSEL1

WAVSEL0

Source

0

0

Active Power signal (output of LPF2)

0

1

RESERVED

1

0

Channel 1

1

1

Channel 2

15

TEST1

Writing a Logic 1 to this bit position places the ADE7756 in test mode. This is intended for

factory testing only and should be left at zero.

MODE REGISTER*

ADDR: 06H

TEST 1

(TEST MODE SELECTION SHOULD BE SET TO 0)

WAVSEL

(WAVE FORM SELECTION FOR SAMPLE MODE)

00 = LPF2

01 = RESERVED

10 = CH1

11 = CH2

DTRT

(WAVE FORM SAMPLES OUTPUT DATA RATE)

00 = 27.9kSPS (CLKIN/128)

01 = 14.4kSPS (CLKIN/256)

10 = 7.2kSPS (CLKIN/512)

11 = 3.6kSPS (CLKIN/1024)

SWAP

(SWAP CH1 AND CH2 ADCs)

DISCH2

(SHORT THE ANALOG INPUTS ON CHANNEL 2)

DISCH1

(SHORT THE ANALOG INPUTS ON CHANNEL 1)

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS

0

000

00

00

7

6

54

32

10

0

000

11

00

8

9

10

11

12

13

14

15

DISHPF

(DISABLE HPF IN CHANNEL 1)

DISLPF2

(DISABLE LPF2 AFTER MULTIPLIER)

DISCF

(DISABLE FREQUENCY OUTPUT CF)

DISSAG

(DISABLE

SAG OUTPUT)

ASUSPEND

(SUSPEND CH1 AND CH2 ADCs)

TEMPSEL

(START TEMPERATURE SENSING)

SWRST

(SOFTWARE CHIP RESET)

CMODE

(CALIBRATION MODE)

Figure 41.