NM1282KSLAXAL datasheet(7/120 Pages) NANYA

7 / 120 page

Version 1.3

Nanya Technology Corp.

06/2018

2Gb SLC NAND + 2Gb LPDDR2

NM1282KSLAXAL

NTC Proprietary

Level: Property

Ball Description - 2Gb X8 SLC NAND

Symbol

Type

Function

X8: I/O[7:0]

Input/output

Data Bus: The I/O0 to 7 pins are used as a port for transferring address, command and input/output data to

and from the device.

CLE

Input

Command Latch Enable: The CLE input signal is used to control loading of the operation mode command

into the internal command register. The command is latched into the command register from the I/O port on

the rising edge of the

 signal while CLE is High.

ALE

Input

Address Latch Enable: The ALE signal is used to control loading address information into the internal

address register. Address information is latched into the address register from the I/O ports on the rising

edge of

 while ALE is High.



Input

Chip Enable: The device goes into a low-power Standby mode when

 goes High during the device is in

Ready state. The

 signal is ignored when device is in Busy state ( RY /  = L), such as during a Program

or Erase or Read operation, and will not enter Standby mode even if the

 input goes High.



Input

Read Enable: The

 signal controls serial data output. Data is available tREA after the falling edge of .

The internal column address counter is also incremented (Address = Address +1) on this falling edge.



Input

Write Enable: The

 signal is used to control the acquisition of data from the I/O port.



Input

Write Protect: The

 signal is used to protect the device from accidental programming or erasing. The

internal voltage regulator is reset when

 is Low. This signal is usually used protecting the data during the

power-on/off sequence when input signals are invalid.

RY/



Output

Ready / Busy Output: The RY /

 output signal is used to indicate the operation condition of the device.

The RY /

 signal is in Busy state ( RY /  =L) during the Program, Erase and Read operations and will

return to Ready state ( RY /

 =H) afeter completion of the operation. The output buffer for this signal is an

open drain and has to be pulled-up to Vccq with an appropriate resister.

If RY /

 signal is not pulled-up to Vccq ( “Open” state ), device operation cannot guarantee.

VCC

Supply

Power

VSS

Supply

Ground

─

No Connect: These pins should be left unconnected.

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