NM1282KSLAXAL datasheet(8/120 Pages) NANYA

8 / 120 page

Version 1.3

Nanya Technology Corp.

06/2018

2Gb SLC NAND + 2Gb LPDDR2

NM1282KSLAXAL

NTC Proprietary

Level: Property

Ball Description - 2Gb X32 LPDDR2

Symbol

Type

Function

CK,



Input

Clock: CK and

 are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on

both positive and negative edge of CK. Single Data Rate (SDR) inputs,

 and CKE, are sampled at the

positive Clock edge. Clock is defined as the differential pair, CK and

. The positive Clock edge is

defined by the crosspoint of a rising CK and a falling

. The negative Clock edge is defined by the

crosspoint of a falling CK and a rising

.

CKE

Input

Clock Enable: CKE high activates, and CKE low deactivates internal clock signals, and device input

buffers and output drivers. Power saving modes are entered and exited through CKE transitions. CKE is

considered part of the command code. CKE is sampled at the positive Clock edge.



Input

Chip Select:

 is considered part of the command code.  is sampled at the positive Clock edge.

CA0

– CA9

Input

Command/Address Inputs: Uni-directional command/address bus inputs. Provide the command and

address inputs according to the command truth table. CA is considered part of the command code.

DM0

– DM3

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled

HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.

Although DM pins are input-only, the DM loading matched the DQ and DQS (or

).

DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on DQ8-DQ15, DM2

corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on DQ24-DQ31.

DQ0-DQ31

Input/output Data Bus: Bi-directional Input / Output data bus.

DQS0-3,

 Input/output

Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for read and write data)

and Differential (DQS and

). It is output with read data and input with write data. DQS is edge-aligned

to read data, and centered with write data.

DQS0 &

 corresponds to the data on DQ0-DQ7, DQS1 &  corresponds to the data on

DQ8-DQ15, DQS2 &

 corresponds to the data on DQ16-DQ23, DQS3 &  corresponds to the

data on DQ24-DQ31.

─

No Connect: No internal electrical connection is present.

Input

Reference Pin for Output Drive Strength Calibration. External impedance (240-ohm): this signal is

used to calibrate the device output impedance.

VDD1

Supply

Core Power Supply 1: Core power supply

VDD2

Supply

Core Power Supply 2: Core power supply

VDDQ

Supply

DQ Power Supply: Isolated on the die for improved noise immunity.

VDDCA

Supply

Input Receiver Power Supply: Power supply for CA0-9, CKE,

, CK, and  input buffers.

VREFDQ, VREFCA

Supply

Reference Voltage: VREFDQ is reference for DQ input buffers. VREFCA is reference for Command /

Address input buffers.

VSS

Supply

Ground

NOTE 1: The signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# =

 = CKb,

/DQS = DQS# =

 = DQSb, /CS = CS# =  = CSb.

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