NM1282KSLAXAL datasheet(28/120 Pages) NANYA

28 / 120 page

Version 1.3

Nanya Technology Corp.

06/2018

2Gb SLC NAND + 2Gb LPDDR2

NM1282KSLAXAL

NTC Proprietary

Level: Property

Auto Page Program Operation with Data Cache

The device has an Auto Page Program with Data Cache operation enabling the high speed program operation

shown below. When the block address changes this

sequenced has to be started from the beginning.

Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache

1 Data for Page N is input to Data Cache.

2 Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (tDCBSYW2).

3 Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache.

4 By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The

device output busy state from the 15h command until the Data Cache becomes empty. The duration of this period depends on timing

between the internal programming of page N and serial data input for Page N + 1 (tDCBSYW2).

5 Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed.

6 The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal

programming of the Page N + P is completed.

NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache

programming is given by the following;

tPROG = tPROG for the last page + tPROG of the previous page − ( command input cycle + address input cycle + data input cycle time of

the last page)

NM1282KSLAXAL 数据表(PDF) 28 Page - Nanya Technology Corporation.