NM1282KSLAXAL datasheet(74/120 Pages) NANYA

74 / 120 page

Version 1.3

Nanya Technology Corp.

06/2018

2Gb SLC NAND + 2Gb LPDDR2

NM1282KSLAXAL

NTC Proprietary

Level: Property

LPDDR2 Descriptions

LPDDR2-S4 uses the double data rate architecture on the Command/Address (CA) bus to reduce the

number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer

information. Each command uses one clock cycle, during which command information is transferred on both

the positive and negative edge of the clock.

To achieve high-speed operation, our LPDDR2-S4 SDRAM uses the double data rate architecture and

adopt 4n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or

write access for the LPDDR2-S4 effectively consists of a single 4n-bit wide, one clock cycle data transfer at

the internal SDRAM core and four corresponding n-bit wide, one-half-clock-cycle data transfer at the I/O

pins. Read and write accesses to the LPDDR2-S4 are burst oriented; accesses start at a selected location

and continue for a programmed number of locations in a programmed sequence.

For LPDDR2-S4 devices, accesses begin with the registration of an Active command, which is then followed

by a Read or Write command. The address and BA bits registered coincident with the Active command are

used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or

Write command are used to select the Bank and the starting column location for the burst access.

NM1282KSLAXAL 数据表(PDF) 74 Page - Nanya Technology Corporation.