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NM1282KSLAXAL 数据表(PDF) 108 Page - Nanya Technology Corporation. |
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NM1282KSLAXAL 数据表(HTML) 108 Page - Nanya Technology Corporation. |
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108 / 120 page  Version 1.3 108 Nanya Technology Corp. 06/2018 All Rights Reserved. © 2Gb SLC NAND + 2Gb LPDDR2 NM1282KSLAXAL NTC Proprietary Level: Property MR4_Device Temperature (MA<7:0> = 04H) MR# MA <7:0> Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 4 04H Refresh Rate R TUF (RFU) Refresh Rate OP<2:0> Refresh Rate Read-only 000B: SDRAM Low temperature operating limit exceeded 001B: 4x tREFI, 4x tREFIpb, 4x tREFW 010B: 2x tREFI, 2x tREFIpb, 2x tREFW 011B: 1x tREFI, 1x tREFIpb, 1x tREFW (<=85C) 100B: RFU 101B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, do not de-rate SDRAM AC timing 110B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, de-rate SDRAM AC timing 111B: SDRAM High temperature operating limit exceeded OP7 TUF (Temperature Update Flag) Read-only 0B: OP<2:0> value has not changed since last read of MR4. 1B: OP<2:0> value has changed since last read of MR4. Notes: 1. A Mode Register Read from MR4 will reset OP7 to “0”. 2. OP7 is reset to “0” at power-up. 3. If OP2 equals “1”, the device temperature is greater than 85C. 4. OP7 is set to “1”, if OP2~OP0 has changed at any time since the last read of MR4. 5. LPDDR2 might not operate properly when OP<2:0> = 000B or 111B. 6. For specified operating temperature range and maximum operating temperature. 7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP and tRRD. The tDQSCK parameter must be derated. Prevailing clock frequency specifications and related setup and hold timings remain unchanged. 8. The recom mended frequency for reading MR4 is provided in “Temperature Sensor”. |
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