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GD25S512MDBJS 数据表(PDF) 30 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD25S512MDBJS
功能描述  3.3V Uniform Sector Dual and Quad Serial Flash
PDF  87 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25S512MDBJS 数据表(HTML) 30 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25S512MD
30
7.12. Dual Output Fast Read (DOFR 3BH or 4DOFR 3CH)
The Dual Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit being
latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 19. The first Byte addressed can be at any location. The address is
automatically incremented to the next higher address after each Byte of data is shifted out.
Figure 19 Dual Output Fast Read Sequence Diagram (ADS=0)
Figure 20 Dual Output Fast Read Sequence Diagram (ADS=1)
Command
0
1
2
3
4
5
6
7
3BH
CS#
SCLK
SI
SO
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
MSB
34 35 36 37
33
5
3
1
7
5
3
1
38 39
Data Out1
32
42 43 44 45
41
46 47
40
7
Data Out2
CS#
SCLK
SI
SO
MSB
Dummy Clocks
4
2
0
6
4
2
0
6
6
7
Command
0
1
2
3
4
5
6
7
3BH
CS#
SCLK
SI
SO
High-Z
8
9 10
36 37 38 39
3
2
1
0
31 30 29
32-bit address
MSB
42 43 44 45
41
5
3
1
46 47
Data Out1
40
50 51 52 53
49
54 55
48
7
6
5
4
3
2
1
0
7
Data Out2
CS#
SCLK
SI
SO
MSB
Dummy Byte
6
4
2
0
5
3
1
7
6
4
2
0
6
7



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