GD25S512MDBJS datasheet(37/87 Pages) GIGADEVICE

37 / 87 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S512MD

Figure 29 Quad I/O Fast Read Sequence Diagram (ADS=1)

Figure 30 Quad I/O Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)

Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The

Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with

Wrap” (77H) commands prior to EBH or ECH. The “Set Burst with Wrap” (77H) command can either enable or disable the

“Wrap Around” feature for the following EBH or ECH commands. When “Wrap Around” is enabled, the data being accessed

can be limited to either an 8/16/32/64-Byte section of a 256-Byte page. The output data starts at the initial address specified

in the command, once it reaches the ending boundary of the 8/16/32/64-Byte section, the output will wrap around the

beginning boundary automatically until CS# is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache

afterwards within a fixed length (8/16/32/64-Byte

) of data without issuing multiple read commands. The “Set Burst with Wrap”

command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation

while W6-W5 is used to specify the length of the wrap around section within a page.

Command

EBH

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16A15-8 A7-0 M7-0

IO2

IO3

Dummy

Byte1 Byte2

A31-24

24 25