GD25S512MDBJS datasheet(14/87 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S512MD

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal

Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or

Erase command is accepted.

TB bit

The Top Bottom (TB) bit is non-volatile (OTP). The Top/Bottom (TB) bit is used to configure the Block Protect area by

BP bit (BP3, BP2, BP1, and BP0), starting from Top or

Bottom of the memory array. The TB bit is defaulted as “0”, which

means Top area protect. When it is set to “1”, the protect area will change to Bottom area of the memory device. This bit is

written with the Write Status Register (WRSR) command.

BP3, BP2, BP1, BP0 bits

The Block Protection (BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software

protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.

When the Block Protect (BP3, BP2, BP1, and BP0) bits are set to 1, the relevant memory area becomes protected against

Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Chip Erase (CE) command is executed, only

if the Block Protect (BP3, BP2, BP1, and BP0) bits are 0.

SRP1, SRP0 bit

The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP

bits control the method of the write protection: software protected, power supply lock-down or one time programmable.

Table 10 Status Register Protect (SRP) bit

SRP1

SRP0

Status Register

Description

Software Protected

The Status Register can be written to after a Write

Enable command, WEL=1.(Default)

Power Supply Lock-Down(1) (2)

Status Register is protected and cannot be written to

again until the nest Power-Down, Power-Up cycle

One Time Program(2)

Status Register is permanently protected and cannot to

written to.

NOTE:

1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available on special order. Please contact GigaDevice for details.

QE bit

The Quad Enable (QE) bit is a non-volatile bit in the Status Register that allows Quad operation. The default value of

QE bit is 1 and it cannot be changed, so that the IO2 and IO3 pins are enabled all the time.

LB3, LB2, LB1, bits.

The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S11, S12, S13) that provide

the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are

unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

SUS1, SUS2 bit

The SUS1 and SUS2 bit are read only bit in the status register (S15 and S10) that are set to 1 after executing an

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