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PCF8811U/2DA/1 数据表(PDF) 50 Page - NXP Semiconductors |
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PCF8811U/2DA/1 数据表(HTML) 50 Page - NXP Semiconductors |
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50 / 73 page  2004 May 17 50 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 20 I2C-BUS INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS =0V; VLCD = maximum 9.0 V; Tamb = −40 °C to +85 °C; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Fs-mode; see Fig.41 fSCLH SCLH clock frequency 0 − 400 kHz tSU;STA set-up time (repeated) START condition 600 −− ns tHD;STA hold time (repeated) START condition 600 −− ns tLOW LOW period of the SCLH clock 1300 −− ns tHIGH HIGH period of the SCLH clock 600 −− ns tSU;DAT data set-up time 100 −− ns tHD;DAT data hold time 0 − 900 ns tr SCL and SDA rise time note 2 20 + 0.1Cb − 300 ns tf SCL and SDA fall time note 2 20 + 0.1Cb − 300 ns Cb capacitive load represented by each bus line −− 400 pF tSU;STO set-up time for STOP condition 600 −− ns tSP tolerable spike width on bus −− 50 ns tBUF bus free time between START and STOP condition 1300 −− ns VnL noise margin at the LOW level for each connected device (including hysteresis) 0.1VDD1 −− V VnH noise margin at the HIGH-level for each connected device (including hysteresis) 0.2VDD1 −− V Hs-mode; see Fig.42 fSCLH SCLH clock frequency 0 − 3.4 MHz tSU;STA set-up time (repeated) START condition 160 −− ns tHD;STA hold time (repeated) START condition 160 −− ns tLOW LOW period of the SCLH clock 160 −− ns tHIGH HIGH period of the SCLH clock 60 −− ns tSU;DAT data set-up time 10 −− ns tHD;DAT data hold time 20 − 70 ns trCL rise time of the SCLH signal 10 − 40 ns trCL1 rise time of the SCLH signal after the acknowledge bit 10 − 80 ns tfCL fall time of the SCLH signal 10 − 40 ns trDA rise time of the SDAH signal 10 − 80 ns tfCL1 fall time of the SCLH signal 10 − 80 ns |
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