PCF8811USLASH2DASLASH1 datasheet(18/73 Pages) PHILIPS

18 / 73 page

2004 May 17

Philips Semiconductors

Product speciﬁcation

× 128 pixels matrix LCD driver

PCF8811

handbook, full pagewidth

RES

SCLK

SDATA

DB7 DB6 DB5 DB4

DB2

DB3

DB1 DB0

SDO

instruction

DB2

DB7 DB6 DB5

DB4 DB3

DB1 DB0

MGW748

read out data

SCE

Fig.16 Read mode SPI 3-line and 4-line.

11.2

Serial interface (3-line)

The serial interface is also a 3-line bidirectional interface

for communication between the microcontroller and the

LCD driver chip. The 3 lines are: SCE (chip enable), SCLK

(serial clock) and SDATA (serial data). The PCF8811 is

connected to the SDA of the microcontroller by two pins:

SDATA (data input) and SDO (data output) which are

connected together.

11.2.1

WRITE MODE

The write mode of the interface means that the

microcontroller writes commands and data to the

PCF8811. Each data packet contains a control bit (D/C)

and a transmission byte. If D/C is LOW, the following byte

is interpreted as a command byte. The command set is

given in Table 5. If D/C is HIGH, the following byte is

stored in the display data RAM. After every data byte the

address counter is incremented automatically. Figure 17

shows the general format of the write mode and the

definition of the transmission byte.

Any instruction can be sent in any order to the PCF8811;

the MSB is transmitted first. The serial interface is

initialized when SCE is HIGH. In this state, SCLK clock

pulses have no effect and no power is consumed by the

serial interface. A falling edge on SCE enables the serial

interface and indicates the start of data transmission.

Figures 18, 19 and 20 show the protocol of the write

mode:

• When SCE is HIGH, SCLK clocks are ignored; during

the HIGH time of SCE the serial interface is initialized

• SCLK must be LOW on the falling SCE edge (see

Fig.37)

• SDATA is sampled on the rising edge of SCLK

• D/C indicates, whether the byte is a command (D/C=0)

or RAM data (D/C = 1); it is sampled on the first rising

SCLK edge

• If SCE stays LOW after the last bit of a command/data

byte, the serial interface receives the D/C bit of the next

byte on the next rising edge of SCLK (see Fig.19)

• A reset pulse RES interrupts the transmission. The data

being written into the RAM may be corrupted. The

registers are cleared. If SCE is LOW after the rising

edge of RES, the serial interface is ready to receive the

D/C bit of a command/data byte (see Fig.20).

PCF8811U/2DA/1 数据表(PDF) 18 Page - NXP Semiconductors

PCF8811U/2DA/1 数据表(HTML) 18 Page - NXP Semiconductors

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