CS5463-ISZ datasheet(20/44 Pages) CIRRUS

20 / 44 page

CS5463

DS678PP1

The temperature update rate is a function of the number

of ADC samples. With MCLK = 4.096 MHz and K = 1

the update rate is:

The Cycle Count Register (N) must be set to a value

greater then one. Status bit TUP in the Status Register,

indicates when the Temperature Register is updated.

The Temperature Offset Register sets the zero-degree

measurement. To improve temperature measurement

accuracy, the zero-degree offset may need to be adjust-

ed after the CS5463 is initialized. Temperature offset

calibration is achieved by adjusting the Temperature

Offset Register

(Toff) by the differential temperature

(

∆T) measured from a calibrated digital thermometer

and the CS5463 temperature sensor. A one degree ad-

justment to the Temperature Register (T) is achieved by

adding 2.737649x10-4 to the Temperature Offset Regis-

ter

(Toff). Therefore,

if Toff = -0.09104831 and ∆T = -7.0 (oC), then

or 0xF419BC (2’s compliment notation) is stored in the

Temperature Offset Register

(Toff).

To convert the Temperature Register (T) from a Celsius

scale (oC) to a Fahrenheit scale (oF) utilize the formula

Applying the above relationship to the CS5461A tem-

perature measurement algorithm

If Toff = -0.09296466 and Tgain = 23.799 for a Celsius

scale, then the modified values are Toff = -0.08809772

(0xF4B937) and Tgain = 42.8382 (0x55AD29) for a

Fahrenheit scale.

5.8 Voltage Reference

The CS5463 is specified for operation with a +2.5 V ref-

erence between the VREFIN and AGND pins. To utilize

the on-chip 2.5 V reference, connect the VREFOUT pin

to the VREFIN pin of the device. The VREFIN can be

used to connect external filtering and/or references.

5.9 System Initialization

Upon powering up, the digital circuitry is held in reset

until the analog voltage reaches 4.0 V. At that time, an

eight XIN clock period delay is enabled to allow the os-

cillator to stabilize. The CS5463 will then initialize.

A hardware reset is initiated when the RESET pin is as-

serted with a minimum pulse width of 50 ns. The RE-

SET signal is asynchronous, with a Schmitt Trigger

input. Once the RESET pin is de-asserted, an eight XIN

clock period delay is enabled.

A software reset is initiated by writing the command

0x80. After a hardware or software reset, the internal

registers (some of which drive output pins) will be reset

to their default values. Status bit DRDY in the Status

indicates the CS5463 is in its active state and

ready to receive commands.

5.10 Power-down States

The CS5463 has two power-down states, Stand-by and

Sleep. In the stand-by state all circuitry except the volt-

age reference and crystal oscillator is turned off. To re-

turn the device to the active state a power-up command

is sent to the device.

In Sleep state all circuitry except the instruction decoder

is turned off. When the power-up command is sent to

the device, a system initialization is performed (See

Section 5.9 System Initialization on page 20).

5.11 Oscillator Characteristics

XIN and XOUT are the input and output of an inverting

amplifier configured as an on-chip oscillator, as shown

in Figure 10. The oscillator circuit is designed to work

with a quartz crystal. To reduce circuit cost, two load ca-

pacitors C1 and C2 are integrated in the device, from

XIN to DGND, and XOUT to DGND. PCB trace lengths

2240 samples

MCLK K

⁄

() 1024

⁄

----------------------------------------

0.56 sec

Toff

∆T 2.737649 10

–

⋅

()

Toff

0.09104831

–

7.0

–

2.737649 10

–

⋅

()

0.09296466

–

---C

17.7778

()

〈〉

--- Tgain

⎝⎠

⎛⎞ TC

〈〉

Toff 17.7778 2.737649

–

⋅

()

⎝⎠

⎛⎞

Oscillator

Circuit

DGND

XIN

XOUT

C1 =

22 pF

C2 =

Figure 10. Oscillator Connection

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