CS5463

DS678PP1

27

Address: 1 (Current DC Offset); 3 (Voltage DC Offset)

Default = 0x000000

register is updated with the DC offset measured over a computation cycle. DRDY will be set at the end of the

calibration. This register may be read and stored for future system offset compensation. The value is represent-

ed in two's complement notation and in the range of -1.0

the MSB. See Section 7.1.2.1 DC Offset Calibration Sequence on page 36 for more information.

Address: 2 (Current Gain); 4 (Voltage Gain)

Default = 0x400000 = 1.000

the register is updated with the gain measured over a computation cycle. DRDY will be set at the end of the

calibration. This register may be read and stored for future system gain compensation. The value is in the range

0.0

6.1.4 Cycle Count Register ( Cycle Count )

Address: 5

Default = 0x000FA0 = 4000

Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,

the computation cycle frequency is (MCLK/K)/(1024

∗N). A one second computational cycle period occurs when

MCLK = 4.096 MHz, K = 1, and N = 4000.

6.1.5 PulseRateE Register ( PulseRateE )

Address: 6

Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)

PulseRateE sets the frequency of E1, E2, & E3

pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at

full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's comple-

ment notation and in the range is -1.0

≤ PulseRateE < 1.0, with the binary point to the right of the MSB. Negative

values have the same effect as positive. See Section 5.5 Energy Pulse Output on page 17 for more information.

MSB

LSB

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MSB

LSB

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MSB

LSB

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MSB

LSB

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