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CS5463-ISZ 数据表(PDF) 24 Page - Cirrus Logic |
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CS5463-ISZ 数据表(HTML) 24 Page - Cirrus Logic |
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24 / 44 page ![]() CS5463 24 DS678PP1 5.15.5 Register Read/Write The Read/Write informs the command decoder that a register access is required. During a read operation, the ad- dressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is clocked into an input buffer and transferred to the addressed register upon completion of the 24th SCLK. W/R Write/Read control 0 = Read 1 = Write RA[4:0] Register address bits (bits 5 through 1) of the read/write command. Register Page 0 Address RA[4:0] Name Description 0 00000 Config Configuration 1 00001 IDCoff Current DC Offset 2 00010 Ign Current Gain 3 00011 VDCoff Voltage DC Offset 4 00100 Vgn Voltage Gain 5 00101 Cycle Count Number of A/D conversions used in one computation cycle (N)). 6 00110 PulseRateE Sets the E1, E2 and E3 energy-to-frequency output pulse rate. 7 00111 I Instantaneous Current 8 01000 V Instantaneous Voltage 9 01001 P Instantaneous Power 10 01010 Pactive Active (Real) Power 11 01011 I RMS RMS Current 12 01100 V RMS RMS Voltage 13 01101 ε (Epsilon) Ratio of line frequency to output word rate (OWR) 14 01110 Poff Power Offset 15 01111 Status Status 16 10000 IACoff Current AC (RMS) Offset 17 10001 VACoff Voltage AC (RMS) Offset 18 10010 Mode Operation Mode 19 10011 T Temperature 20 10100 Q AVG Average Reactive Power 21 10101 Q Instantaneous Reactive Power 22 10101 I Peak Peak Current 23 10111 V Peak Peak Voltage 24 11000 Q Trig Reactive Power calculated from Power Triangle 25 11001 PF Power Factor 26 11010 Mask Interrupt Mask 27 11011 S Apparent Power 28 11100 Ctrl Control 29 11101 P H Harmonic Active Power 30 11110 P F Fundamental Active Power 31 11111 Q F Fundamental Reactive Power / Page Note: For proper operation, do not attempt to write to unspecified registers. B7 B6 B5 B4 B3 B2 B1 B0 0W/R RA4 RA3 RA2 RA1 RA0 0 |
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