USB3280

DS00001898A-page 18

 2004 - 2015 Microchip Technology Inc.

Figure 7-2 shows the relationship between CLKOUT and the receive data control signals in FS mode. RXACTIVE

"frames" a packet, transitioning only at the beginning and end of a packet. However transitions of RXVALID may take

place any time 8 bits of data are available. Figure 7-1 also shows how RXVALID is only asserted for one CLKOUT cycle

per byte time even though the data may be presented for the full byte time. The XCVRSELECT signal determines

whether the HS or FS timing relationship is applied to the data and control signals.

7.3

Clock and Data Recovery Circuit

This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity Buffer is used to com-

pensate for differences between the transmitting and receiving clock domains. The USB 2.0 specification defines a max-

imum clock error of ±1000ppm of drift.

7.4

TX Logic

This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit operations. These

operations include parallel to serial conversion, bit stuffing and NRZI encoding. Upon valid assertion of the proper TX

control lines by the SIE and TX State Machine, the TX LOGIC block will synchronously shift, at either the FS or HS rate,

the data to the FS/HS TX block to be transmitted on the USB cable. Data transmit timing is shown in Figure 7-3.

The behavior of the Transmit State Machine is described below.

• Asserting a RESET forces the transmit state machine into the Reset state which negates TXREADY. When

RESET is negated the transmit state machine will enter a wait state.

• The SIE asserts TXVALID to begin a transmission.

• After the SIE asserts TXVALID it can assume that the transmission has started when it detects TXREADY has

been asserted.

FIGURE 7-2:

FS CLK RELATIONSHIP TO RECEIVE DATA AND CONTROL SIGNALS

FIGURE 7-3:

TRANSMIT TIMING FOR A DATA PACKET