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DS00001898A-page 19

USB3280

• The SIE must assume that the USB3280 has consumed a data byte if TXREADY and TXVALID are asserted on

the rising edge of CLKOUT.

• The SIE must have valid packet information (PID) asserted on the DATA bus coincident with the assertion of

TXVALID.

• TXREADY is sampled by the SIE on the rising edge of CLKOUT.

• The SIE negates TXVALID to complete a packet. Once negated, the transmit logic will never reassert TXREADY

until after the EOP has been generated. (TXREADY will not re-assert until TXVALD asserts again.

• The USB3280 is ready to transmit another packet immediately, however the SIE must conform to the minimum

inter-packet delays identified in the USB 2.0 specification.

7.5

RX Logic

This block receives serial data from the CRC block and processes it to be transferred to the SIE on the DATA bus. The

processing involved includes NRZI decoding, bit unstuffing, and serial to parallel conversion. Upon valid assertion of the

proper RX control lines by the RX State Machine, the RX Logic block will provide bytes to the DATA bus as shown in

the figures below. The behavior of the Receive State Machine is described below.

The assertion of RESET will force the Receive State Machine into the Reset state. The Reset state deasserts RXAC-

TIVE and RXVALID. When the RESET signal is deasserted the Receive State Machine enters the RX Wait state and

starts looking for a SYNC pattern on the USB. When a SYNC pattern is detected the state machine will enter the Strip

SYNC

state and assert RXACTIVE. The length of the received Hi-Speed SYNC pattern varies and can be up to 32 bits

long or as short as 12 bits long when at the end of five hubs. As a result, the state machine may remain in the Strip

SYNC

state for several byte times before capturing the first byte of data and entering the RX Data state.

After valid serial data is received, the state machine enters the RX Data state, where the data is loaded into the RX

Holding Register on the rising edge of CLKOUT and RXVALID is asserted. The SIE must clock the data off the DATA

bus on the next rising edge of CLKOUT. If OPMODE = Normal, then stuffed bits are stripped from the data stream. Each

time 8 stuffed bits are accumulated the state machine will enter the RX Data Wait state, negating RXVALID thus skipping

a byte time.

When the EOP is detected the state machine will enter the Strip EOP state and negate RXACTIVE and RXVALID. After

the EOP has been stripped the Receive State Machine will reenter the RX Wait state and begin looking for the next

packet.

The behavior of the Receive State Machine is described below:

• RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.

• In the RX Wait state the receiver is always looking for SYNC.

• The USB3280 asserts RXACTIVE when SYNC is detected (Strip SYNC state).

• The USB3280 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty (Strip EOP state).

• When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.

• RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur

if 8 stuffed bits have been accumulated.

FIGURE 7-4:

RECEIVE TIMING FOR DATA WITH UNSTUFFED BITS