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DS00001898A-page 31

USB3280

Note 1:

T0 may be up to 4ms after HS Reset T0.

2:

The SIE must use LINESTATE to detect the downstream port chirp sequence.

3:

Due to the assertion of the HS termination on the host port and FS termination on the device port, between

T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are less than FS signaling

levels.

FIGURE 8-5:

HS DETECTION HANDSHAKE TIMING BEHAVIOR (HS MODE)

TABLE 8-7:

RESET TIMING VALUES

Timing Parameter

Description

Value

T0

HS Handshake begins. DP pull-up enabled, HS

terminations disabled.

0 (reference)

T1

Device asserts Chirp K on the bus.

T0 < T1 < HS Reset T0 + 6.0ms

T2

Device removes Chirp K from the bus. 1 ms minimum

width.

T0 + 1.0ms < T2 <

HS Reset T0 + 7.0ms

T3

Downstream facing port asserts Chirp K on the bus. T2 < T3 < T2+100µs

T4

Downstream facing port toggles Chirp K to Chirp J on

the bus.

T3 + 40µs < T4 < T3 + 60µs

T5

Downstream facing port toggles Chirp J to Chirp K on

the bus.

T4 + 40µs < T5 < T4 + 60µs

T6

Device detects downstream port chirp.

T6

T7

Chirp detected by the device. Device removes DP

pull-up and asserts HS terminations, reverts to HS

default state and waits for end of reset.

T6 < T7 < T6 + 500µs

T8

Terminate host port Chirp K-J sequence (Repeating

T4 and T5)

T9 - 500µs < T8 < T9 - 100µs

T9

The earliest time at which host port may end reset.

The latest time, at which the device may remove the

DP pull-up and assert the HS terminations, reverts to

HS default state.

HS Reset T0 + 10ms