USB3280

DS00001898A-page 28

 2004 - 2015 Microchip Technology Inc.

8.7

HS Detection Handshake

The High Speed Detection Handshake process is entered from one of three states: suspend, active FS or active HS.

The downstream facing port asserting an SE0 state on the bus initiates the HS Detection Handshake. Depending on

the initial state, an SE0 condition can be asserted from 0 to 4 ms before initiating the HS Detection Handshake. These

states are described in the USB 2.0 specification.

There are three ways in which a device may enter the HS Handshake Detection process:

1.

If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS handshake

detection process.

2.

If the device is in FS mode and an SE0 state is detected for more than 2.5µs. it may enter the HS handshake

detection process.

3.

If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the HS handshake

detection process. In HS mode, a device must first determine whether the SE0 state is signaling a suspend or a

reset condition. To do this the device reverts to FS mode by placing XCVRSELECT and TERMSELECT into FS

mode. The device must not wait more than 3.125ms before the reversion to FS mode. After reverting to FS mode,

no less than 100µs and no more than 875µs later the SIE must check the LINESTATE signals. If a J state is

detected the device will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Hand-

shake detection process.

In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval is 10ms. Depend-

ing on the previous mode that the bus was in, the delay between the initial assertion of the SE0 state and entering the

HS Handshake detection can be from 0 to 4ms.

This transceiver design pushes as much of the responsibility for timing events on to the SIE as possible, and the SIE

requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3 above, CLKOUT has been running and is

stable, however in case 1 the USB3280 is reset from a suspend state, and the internal oscillator and clocks of the trans-

ceiver are assumed to be powered down. A device has up to 6ms after the release of SUSPENDN to assert a minimum

of a 1ms Chirp K.