USB3280

DS00001898A-page 22

 2004 - 2015 Microchip Technology Inc.

7.6.3

BIAS GENERATOR

This block consists of an internal bandgap reference circuit used for generating the high speed driver currents and the

biasing of the analog circuits. This block requires an external 12k

Ω, 1% tolerance, external reference resistor connected

from RBIAS to ground.

7.7

Crystal Oscillator and PLL

The USB3280 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is

used by the PHY during both transmit and receive. The USB3280 requires a clean 24MHz crystal or clock as a frequency

reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly.

The USB3280 can use either a crystal or an external clock oscillator for the 24MHz reference. The crystal is connected

to the XI and XO pins as shown in the application diagram, Figure 8-9. If a clock oscillator is used the clock should be

connected to the XI input and the XO pin left floating. When a external clock is used the XI pin is designed to be driven

with a 0 to 3.3 volt signal. When using an external clock the user needs to take care to ensure the external clock source

is clean enough to not degrade the high speed eye performance.

Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz clock.

7.8

Internal Regulators and POR

The USB3280 includes an integrated set of built in power management functions. These power management features

include a POR generation and allow the USB3280 to be powered from a single 3.3 volt power supply. This reduces the

bill of materials and simplifies product design.

7.8.1

INTERNAL REGULATORS

The USB3280 has two integrated 3.3 volt to 1.8 volt regulators. These regulators require an external 4.7uF +/-20% low

ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since they exhibit an ESR

lower than 0.1 ohm at frequencies greater than 10kHz.

The two regulator outputs, which require bypass capacitors, are the pins labeled VDDA1.8 and VDD1.8. Each pin

requires a 4.7uF bypass capacitor placed as close to the pin as possible.

TABLE 7-1:

DP/DM TERMINATION VS. SIGNALING MODE

Signaling Mode

UTMI+ Interface Settings

Resistor Settings

Tri-State Drivers

Xb

Xb

01b

0b

0b

Power-up

1b

0b

00b

0b

0b

Peripheral Chirp

0b

1b

10b

1b

0b

Peripheral HS

0b

0b

00b

0b

1b

Peripheral FS

1b

1b

00b

1b

0b

Peripheral HS/FS Suspend

1b

1b

00b

1b

0b

Peripheral HS/FS Resume

1b

1b

10b

1b

0b

Peripheral Test J/Test K

0b

0b

10b

0b

1b

Note:

The USB3280 regulators are designed to generate a 1.8 volt supply for the USB3280 only. Using the reg-

ulators to provide current for other circuits is not recommended and Microchip does not guarantee USB

performance or regulator stability.