USB3280

DS00001898A-page 20

 2004 - 2015 Microchip Technology Inc.

• The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data state).

• Figure 7-5 shows the timing relationship between the received data (DP/DM), RXVALID, RXACTIVE, RXERROR

and DATA signals.

Note 1:

The USB 2.0 Transceiver does NOT decode Packet ID's (PIDs). They are passed to the SIE for decoding.

2:

Figure 7-5, Figure 7-6 and Figure 7-7 are timing examples of a HS/FS PHY when it is in HS mode. When a

HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time. The Receive State

Machine assumes that the SIE captures the data on the DATA bus if RXACTIVE and RXVALID are asserted.

In FS mode, RXVALID will only be asserted for one CLKOUT per byte time.

3:

In Figure 7-5, Figure 7-6 and Figure 7-7 the SYNC pattern on DP/DM is shown as one byte long. The SYNC

pattern received by a device can vary in length. These figures assume that all but the last 12 bits have been

consumed by the hubs between the device and the host controller.

FIGURE 7-5:

RECEIVE TIMING FOR A HANDSHAKE PACKET (NO CRC)

FIGURE 7-6:

RECEIVE TIMING FOR SETUP PACKET