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FS32K142BHTXVLLTR 数据表(PDF) 51 Page - NXP Semiconductors |
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FS32K142BHTXVLLTR 数据表(HTML) 51 Page - NXP Semiconductors |
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51 / 100 page ![]() Table 39. QuadSPI electrical specifications FLASH PORT Sym Unit FLASH A FLASH B RUN1 HSRUN1 RUN/HSRUN2 QuadSPI Mode SDR SDR SDR DDR3 Internal Sampling Internal DQS Internal Sampling Internal DQS Internal Sampling External DQS N1 PAD Loopback Internal Loopback N1 PAD Loopback Internal Loopback N1 External DQS Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Register Settings MCR[DDR_EN] - 0 0 0 0 0 0 0 1 MCR[DQS_EN] - 0 1 1 0 1 1 0 1 MCR[SCLKCFG[0]] - - 1 0 - 1 0 - - MCR[SCLKCFG[1]] - - 1 0 - 1 0 - - MCR[SCLKCFG[2]] - - - - - - - - 0 MCR[SCLKCFG[3]] - - - - - - - - 0 MCR[SCLKCFG[5]] - 0 0 0 0 0 0 0 1 SMPR[FSPHS] - 0 1 0 0 1 0 0 0 SMPR[FSDLY] - 0 0 0 0 0 0 0 0 SOCCR [SOCCFG[7:0]] - 0 23 - 0 30 - - SOCCR[SOCCFG[15:8]] - - - - - - - - 30 FLSHCR[TDH] - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 Timing Parameters SCK Clock Frequency fSCK MHz - 38 - 64 - 48 - 40 - 80 - 50 - 20 - 204 SCK Clock Period tSCK ns - - - - - - 50.0 - 50.04 - Table continues on the next page... |
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