 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
FS32K142BHTXVLLTR 数据表(PDF) 78 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
FS32K142BHTXVLLTR 数据表(HTML) 78 Page - NXP Semiconductors |
|
|
78 / 100 page  Table 52. SWD electrical specifications Symbo l Description Run Mode HSRUN Mode VLPR Mode (S32K1xx) VLPR Mode (S32K14xW) Unit 5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. S1 SWD_CLK frequency of operation - 25 - 25 - 25 - 25 - 10 - 10 - 1 - 1 MHz S2 SWD_CLK cycle period 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - ns S3 SWD_CLK clock pulse width ns S4 SWD_CLK rise and fall times - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 ns S9 SWD_DIO input data setup time to SWD_CLK rise 4 - 4 - 4 - 4 - 16 - 16 - 30 - 30 - ns S10 SWD_DIO input data hold time after SWD_CLK rise 3 - 3 - 3 - 3 - 10 - 10 - 19 - 19 - ns S11 SWD_CLK high to SWD_DIO data valid - 28 - 38 - 28 - 38 - 70 - 77 - 180 - 180 ns S12 SWD_CLK high to SWD_DIO high-Z - 28 - 38 - 28 - 38 - 70 - 77 - 180 - 180 ns S13 SWD_CLK high to SWD_DIO data invalid 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ns |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
