FS32K142BHTXVLLTR datasheet(74/100 Pages) NXP

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S21

S19

S17

S15

S16

S17

S18

S22

S20

S18

S13

S14

SAI_BCLK (input)

SAI_FS (output)

SAI_FS (input)

SAI_TXD

SAI_RXD

Figure 24. SAI Timing — Slave modes

6.5.6 Ethernet AC specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

The following table describes the MII electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and

pad configured with fastest slew settings (DSE = 1'b1).

• I/O operating voltage ranges from 2.97 V to 3.6 V

• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the

interface should be OFF.

Table 49. MII signal switching specifications

Symbol

Description

Min.

Max.

Unit

—

RXCLK frequency

—

MHz

MII1

RXCLK pulse width high

35%

65%

RXCLK period

MII2

RXCLK pulse width low

35%

65%

RXCLK period

MII3

RXD[3:0], RXDV, RXER to RXCLK setup

—

MII4

RXCLK to RXD[3:0], RXDV, RXER hold

—

TXCLK frequency

—

MHz

MII5

TXCLK pulse width high

35%

65%

TXCLK period

MII6

TXCLK pulse width low

35%

65%

TXCLK period

MII7

TXCLK to TXD[3:0], TXEN, TXER invalid

—

MII8

TXCLK to TXD[3:0], TXEN, TXER valid

—

Communication modules

S32K1xx Data Sheet, Rev. 12, 02/2020

NXP Semiconductors

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