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数据搜索系统，热门电子元器件搜索 |
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IIS2DLPC 数据表(PDF) 51 Page - STMicroelectronics |
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IIS2DLPC 数据表(HTML) 51 Page - STMicroelectronics |
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51 / 69 page  DocID031788 Rev 4 51/69 IIS2DLPC Register description 69 8.7 CTRL4_INT1_PAD_CTRL (23h) Control register 4 (r/w) Table 38. Control register 4 Table 39. Control register 4description INT1_6D INT1_ SINGLE _TAP INT1_WU INT1_FF INT1_TAP INT1_ DIFF5 INT1_ FTH INT1_ DRDY INT1_6D 6D recognition is routed to INT1 pad. Default: 0 (0: disabled; 1: enabled) INT1_SINGLE_TAP Single-tap recognition is routed to INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_WU Wakeup recognition is routed to INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_FF Free-fall recognition is routed to INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_TAP Double-tap recognition is routed to INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_DIFF5 FIFO full recognition is routed to INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_FTH FIFO threshold interrupt is routed to INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_DRDY Data-Ready is routed to INT1 pad. Default value: 0 (0: disabled; 1: enabled) |
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