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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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IIS2DLPC 数据表(PDF) 52 Page - STMicroelectronics |
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IIS2DLPC 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 69 page  Register description IIS2DLPC 52/69 DocID031788 Rev 4 8.8 CTRL5_INT2_PAD_CTRL (24h) Control register 5 (r/w) Table 40. Control register 5 Table 41. Control register 5 description INT2_ SLEEP_ STATE INT2_ SLEEP_ CHG INT2_ BOOT INT2_ DRDY_T INT2_ OVR INT2_ DIFF5 INT2_ FTH INT2_ DRDY INT2_SLEEP_STATE Enable routing of SLEEP_STATE on INT2 pad. Default value: 0 (0: disabled; 1: enabled) INT2_SLEEP_CHG Sleep change status routed to INT2 pad. Default value: 0 (0: disabled; 1: enabled) INT2 _BOOT Boot state routed to INT2 pad. Default value: 0 (0: disabled; 1: enabled) INT2_DRDY_T Temperature data-ready is routed to INT2. Default value: 0 (0: disabled; 1: enabled) INT2 _OVR FIFO overrun interrupt is routed to INT2 pad. Default value: 0 (0: disabled; 1: enabled) INT2_DIFF5 FIFO full recognition is routed to INT2 pad. Default value: 0 (0: disabled; 1: enabled) INT2 _FTH FIFO threshold interrupt is routed to INT2 pad. Default value: 0 (0: disabled; 1: enabled) INT2 _DRDY Data-ready is routed to INT2 pad. Default value: 0 (0: disabled; 1: enabled) |
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