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IIS2DLPC 数据表(PDF) 65 Page - STMicroelectronics |
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IIS2DLPC 数据表(HTML) 65 Page - STMicroelectronics |
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65 / 69 page ![]() DocID031788 Rev 4 65/69 IIS2DLPC Register description 69 8.35 CTRL7 (3Fh) Table 94. CTRL7 register Table 95. CTRL7 register description DRDY_ PULSED INT2_ON _INT1 INTERRUPTS _ENABLE USR_OFF _ON_OUT USR_OFF _ON_WU USR_OFF _W HP_REF _MODE LPASS_ ON6D DRDY_ PULSED Switches between latched and pulsed mode for data ready interrupt. (0: latched mode is used; 1: pulsed mode enabled for data-ready) INT2_ON_INT1 Signal routing. (1: all signals available only on INT2 are routed on INT1) INTERRUPTS_ ENABLE Enable interrupts. USR_OFF _ON_OUT Enable application of user offset value on XL output data registers. FDS bit in CTRL6 (25h) must be set to '0'-logic (low-pass path selected). USR_OFF _ON_WU Enable application of user offset value on XL data for wakeup function only. USR_OFF_W Selects the weight of the user offset words specified by X_OFS_USR_[7:0], Y_OFS_USR_[7:0] and Z_OFS_USR_[7:0] bits. (0: 977 μg/LSB; 1: 15.6 mg/LSB) HP_REF_MODE High-pass filter reference mode enable. (0: high-pass filter reference mode disabled (default); 1: high-pass filter reference mode enabled) LPASS_ON6D (0: ODR/2 low pass filtered data sent to 6D interrupt function (default); 1: LPF2 output data sent to 6D interrupt function) |
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